Rainbow Electronics DS2154 - Manual (Page 24)

DS2154
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CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex)
(MSB) (LSB)
LIRST – – RCM4 RCM3 RCM2 RCM1 RCM0
SYMBOL POSITION NAME AND DESCRIPTION
LIRST CCR5.7 Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that affects the clock recovery state machine and jitter attenu-
ator. Normally this bit is only toggled on power–up. Must be cleared and set
again for a subsequent reset.
– CCR5.6 Not Assigned. Should be set to zero when written
– CCR5.5 Not Assigned. Should be set to zero when written.
RCM4 CCR5.4 Receive Channel Monitor Bit 4. MSB of a channel decode that deter-
mines which receive channel data will appear in the RDS0M register. See
Section 6 for details.
RCM3 CCR5.3 Receive Channel Monitor Bit 3.
RCM2 CCR5.2 Receive Channel Monitor Bit 2.
RCM1 CCR5.1 Receive Channel Monitor Bit 1.
RCM0 CCR5.0 Receive Channel Monitor Bit 0. LSB of the channel decode.
4.0 STATUS AND INFORMATION
REGISTERS
There is a set of four registers that contain information
on the current real time status of the DS2154, Status
Register 1 (SR1), Status Register 2 (SR2), Receive
Information Register (RIR), and Synchronizer Status
Register (SSR). When a particular event has occurred
(or is occuring), the appropriate bit in one of these four
registers will be set to a one. All of the bits in these regis-
ters operate in a latched fashion (except for the SSR).
This means that if an event or an alarm occurs and a bit
is set to a one in any of the registers, it will remain set
until the user reads that bit. The bit will be cleared when
it is read and it will not be set again until the event has
occurred again (or in the case of the RUA1, RRA, RCL,
and RLOS alarms, the bit will remain set if the alarm is
still present).
The user will always precede a read of the SR1, SR2,
and RIR registers with a write. The byte written to the
register will inform the DS2154 which bits the user
wishes to read and have cleared. The user will write a
byte to one of these three registers, with a one in the bit
positions he or she wishes to read and a zero in the bit
positions he or she does not wish to obtain the latest
information on. When a one is written to a bit location,
the read register will be updated with the latest informa-
tion. When a zero is written to a bit position, the read
register will not be updated and the previous value will
be held. A write to the status and information registers
will be immediately followed by a read of the same regis-
ter. The read result should be logically AND’ed with the
mask byte that was just written and this value should be
written back into the same register to insure that bit does
indeed clear. This second write step is necessary
because the alarms and events in the status registers
occur asynchronously in respect to their access via the
parallel port. This write–read–write scheme allows an
external microcontroller or microprocessor to individu-
ally poll certain bits without disturbing the other bits in
the register. This operation is key in controlling the
DS2154 with higher–order software languages.
The SSR register operates differently than the other
three. It is a read only register and it reports the status of
the synchronizer in real time. This register is not latched
and it is not necessary to precede a read of this register
with a write.
The SR1 and SR2 registers have the unique ability to
initiate a hardware interrupt via the INT output pin. Each
of the alarms and events in the SR1 and SR2 can be
either masked or unmasked from the interrupt pins via
the Interrupt Mask Register 1 (IMR1) and Interrupt Mask
Register 2 (IMR2) respectively.
The interrupts caused by alarms in SR1 (namely RUA1,
RRA, RCL, and RLOS) act differently than the interrupts