Rainbow Electronics DS2154 - Manual (Page 25)

DS2154
031197 25/69
caused by events in SR1 and SR2 (namely RSA1,
RDMA, RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF,
LOTC, RCMF, and TSLIP). The alarm caused interrupts
will force the INT pin low whenever the alarm changes
state (i.e. the alarm goes active or inactive according to
the set/clear criteria in Table 4–1). The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the inter-
rupt to occur even if the alarm is still present.
The event caused interrupts will force the INT pin low
when the event occurs. The INT pin will be allowed to
return high (if no other interrupts are present) when the
user reads the event bit that caused the interrupt to
occur.
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB) (LSB)
TESF TESE JALT RESF RESE CRCRC FASRC CASRC
SYMBOL POSITION NAME AND DESCRIPTION
TESF RIR.7 Transmit Side Elastic Store Full. Set when the transmit side elastic store
buffer fills and a frame is deleted.
TESE RIR.6 Transmit Side Elastic Store Empty. Set when the transmit side elastic
store buffer empties and a frame is repeated.
JALT RIR.5 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to
within 4–bits of its limit; useful for debugging jitter attenuation operation.
RESF RIR.4 Receive Side Elastic Store Full. Set when the receive side elastic store
buffer fills and a frame is deleted.
RESE RIR.3 Receive Side Elastic Store Empty. Set when the receive side elastic
store buffer empties and a frame is repeated.
CRCRC RIR.2 CRC Resync Criteria Met. Set when 915/1000 code words are received in
error.
FASRC RIR.1 FAS Resync Criteria Met. Set when 3 consecutive FAS words are
received in error.
CASRC RIR.0 CAS Resync Criteria Met. Set when 2 consecutive CAS MF alignment
words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB) (LSB)
CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA
SYMBOL POSITION NAME AND DESCRIPTION
CSC5 SSR.7 CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.
CSC4 SSR.6 CRC4 Sync Counter Bit 4.
CSC3 SSR.5 CRC4 Sync Counter Bit 3.
CSC2 SSR.4 CRC4 Sync Counter Bit 2.
CSC0 SSR.3 CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next to LSB is
not accessible.