Rainbow Electronics AT75C310 - Manual (Page 9)

AT75C310
9
Initialization
Reset initializes the user interface registers to their default
states as defined in the peripheral sections of this
datasheet and forces the ARM7TDMI to perform the next
instruction fetch from address zero. Except for the program
counter, the ARM core registers do not have defined reset
states. When reset is active, the inputs of the AT75C310
must be held at valid logic levels.
There are three ways in which the AT75C310 can enter
reset:
1. Hardware reset. Caused by asserting the RESET
pin, e.g., at power-up.
2. Watchdog timer reset. The watchdog timer can be
programmed so that if it is timed out, a pulse is gen-
erated that forces a chip reset.
3. Software reset. There are two software resets which
are asserted by writing to bits [11:10] of the
AT75C310 mode register. SIAP_MD[11] forces a
software reset with RM set low and SIAP_MD[10]
forces a reset with RM set high.
Reset Pin
The reset pin should be asserted for a minimum of 10 clock
cycles. However, if external DRAM is fitted, reset should be
applied for the time interval specified by the DRAM
datasheet, typically 200 µs. The OakDSPCores are only
released from reset by ARM program control.
When reset is released, the pin NDSRA/BOOTN is sam-
pled to determine if the ARM should boot from internal
ROM or from external memory connected to NCS0. The
details of this boot operation are described in the section
“Boot Mode” on page 11.
Processor Synchronization
The ARM and the OakDSPCore processors have their own
PLLs and at power-on each processor has its own indeter-
minate lock period. To guarantee proper synchronization of
inter-processor communication through the mailboxes, a
specific reset sequence should be followed.
Once the ARM core is out of reset, it should set and clear
the reset line of each OakDSPCore three times. This guar-
antees message synchronization between the ARM and
the OakDSPCores.