Spi receive data register – Rainbow Electronics AT75C310 User Manual

Page 110

AT75C310

110

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PCS: Peripheral Chip Select

This field is only used if Fixed Peripheral Select is active (PS=0).

If PCSDEC=0:

PCS = xxx0

NPCS[3:0] = 1110

PCS = xx01

NPCS[3:0] = 1101

PCS = x011

NPCS[3:0] = 1011

PCS = 0111 NPCS[3:0] = 0111

PCS = 1111 forbidden (no peripheral is selected)

(x = don’t care)

If PCSDEC=1:

NPCS[3:0] output signals = PCS

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DLYBCS: Delay Between Chip Selects

This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals having long data float times.

If DLYBCS is less than or equal to six, six SPI master clock periods will be inserted by default.

Otherwise, the following equation determines the delay:

SPI Receive Data Register

Register Name:

SP_RDR

Access Type:

Read-only

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RD: Receive Data

Data received by the SPI interface is stored in this register right-justified. Unused bits read zero.

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PCS: Peripheral Chip Select Status

In master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read
as zero.

Delay_Between_Chip_Selects

DLYBCS

SPI_Master_Clock_Period

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PCS