Rainbow Electronics AT75C310 - Manual (Page 6)

AT75C310
6
Architectural Overview
The AT75C310 architecture consists of two main buses,
the Advanced System Bus (ASB) and the Advanced
Peripheral Bus (APB).
The ASB is designed for maximum performance. It inter-
faces the processor with the on-chip DSP subsystems and
the external memories and devices by means of the Exter-
nal Bus Interface (EBI).
The APB is designed for accesses to on-chip peripherals
and is optimized for low power consumption. The AMBA
™
Bridge provides an interface between the ASB and the
APB.
An on-chip Peripheral Data Controller (PDC) transfers data
between the on-chip USARTs and the memories without
processor intervention. Most importantly, the PDC removes
the processor interrupt handling overhead and significantly
reduces the number of clock cycles required for a data
transfer. It can transfer up to 64K contiguous bytes without
reprogramming the starting address. As a result, microcon-
troller performance is increased and power consumption
reduced.
The AT75C310 peripherals are designed to be pro-
grammed with a minimum number of instructions. Each
peripheral has a 16 KB address space allocated in the
upper part of the address space. The peripheral register set
is composed of control, mode, data, status and interrupt
registers.
To maximize the efficiency of bit manipulation, frequently-
written registers are mapped into three memory locations.
The first address is used to set the individual register bits,
the second resets the bits and the third address reads the
value stored in the register. A bit can be set or reset by writ-
ing a one to the corresponding position at the appropriate
address. Writing a zero has no effect. Individual bits can
thus be modified without having to use costly read-modify-
write and complex bit-manipulation instructions, and with-
out having to store-disable-restore the interrupt state.
All external signals of the on-chip peripherals are controlled
by the parallel I/O controllers. The PIO controllers can be
programmed to insert an input filter on each pin or to gener-
ate an interrupt on a signal change. After reset, the user
must carefully program the PIO controllers in order to
define which peripheral signals are connected with off-chip
logic.
The ARM7TDMI processor operates in little-endian mode
in the AT75C310. The processor’s internal architecture and
the ARM and Thumb instruction sets are described in the-
Atmel ARM7TDMI datasheet, literature number 0673. The
memory map and the on-chip peripherals are described in
this datasheet. The DSP subsystems are described in the
datasheet entitled “AT75C310 DSP Subsystem”, literature
number 1368. Electrical characteristics are documented in
a separate datasheet entitled “AT75C310 Electrical and
Mechanical Characteristics”, literature number 1370.
PDC: Peripheral Data Controller
The AT75C310 has a four-channel PDC dedicated to the
two on-chip USARTs. One PDC channel is connected to
the receiving channel and one to the transmitting channel
of each USART.
The user interface of a PDC channel is integrated in the
memory space of each USART channel. It contains a 32-bit
address pointer register and a 16-bit count register. When
the programmed number of bytes is transferred, an end of
transfer interrupt is generated by the corresponding
USART. For more details on PDC operation and program-
ming, see the section “USART: Universal Synchro-
nous/Asynchronous Receiver/Transmitter” on page 53.