Rainbow Electronics AT75C310 - Manual (Page 31)

AT75C310
31
Priority Controller
The NIRQ line is controlled by an eight-level priority
encoder. Each source has a programmable priority level of
7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt
at a time, the interrupt with the highest priority is serviced
first. If both interrupts have equal priority, the interrupt with
the lowest interrupt source number is serviced first. Inter-
rupt source numbers are given in Table 11.
The current priority level is defined as the priority level of
the current interrupt at the time the register AIC_IVR is
read (the interrupt which will be serviced).
If a higher priority unmasked interrupt occurs and an inter-
rupt already exists, there are two possible outcomes
depending on whether the AIC_IVR has been read.
1. If the NIRQ line has been asserted but the AIC_IVR
has not been read, then the processor will read the
new higher priority interrupt handler address in the
AIC_IVR register and the current interrupt level is
updated.
2. If the processor has already read the AIC_IVR, then
the NIRQ line is reasserted. When the processor
has authorized nested interrupts to occur and reads
the AIC_IVR again, it reads the new, higher-priority
interrupt handler address. At the same time, the
current priority value is pushed onto a first-in last-
out stack and the current priority is updated to the
higher priority.
W h e n t h e E n d o f I n t e r r u p t C o m m a n d R e g i s t e r
(AIC_EOICR) is written, the current interrupt level is
updated with the last stored interrupt level from the stack (if
any). Hence, at the end of a higher priority interrupt, the
AIC returns to the previous state corresponding to the pre-
ceding lower priority interrupt which had been interrupted.
Interrupt Handling
The interrupt handler must read the AIC_IVR as soon as
possible. This de-asserts the NIRQ request to the proces-
sor and clears the interrupt in case it is programmed to be
edge-triggered. This permits the AIC to assert the NIRQ
line again when a higher-priority unmasked interrupt
occurs.
At the end of the interrupt service routine, the End of Inter-
rupt Command Register (AIC_EOICR) must be written.
This allows pending interrupts to be serviced.
Interrupt Masking
Each interrupt source, including FIQ, can be enabled or
disabled using the command registers AIC_IECR and
AIC_IDCR. The interrupt mask can be read in the read-only
register AIC_IMR. A disabled interrupt does not affect the
servicing of other interrupts.
Interrupt Clearing and Setting
All interrupt sources which are programmed to be edge-
triggered (including FIQ) can be individually set or cleared
by writing to the registers AIC_ISCR and AIC_ICCR,
respectively. This function of the interrupt controller is avail-
able for auto-test or software debug purposes.
Fast Interrupt Request
The external FIQ line is the only source which can raise a
fast interrupt request to the processor. Therefore, it has no
priority controller.
The external FIQ line can be programmed to be positive- or
negative-edge triggered or high- or low-level sensitive in
the AIC_SMR0 register.
The interrupt handler can be stored starting from address
0x0000001C as described in the Atmel ARM7TDMI
datasheet, literature number 0673.
Software Interrupt
Interrupt source 1 of the AIC is a software interrupt. It must
be programmed to be edge-triggered in order to set or clear
it by writing to the AIC_ISCR and AIC_ICCR.
T h i s i s i n d e p e n d e n t o f t h e S W I i n s t r u c t i o n o f t h e
ARM7TDMI processor.
Standard Interrupt Sequence
The following conditions are assumed:
• The AIC has been programmed and interrupts are
enabled.
• The instruction at address 0x18 (IRQ exception vector
address) jumps into a default handler which reads
AIC_IVR and then jumps to the specific service routine
for the read interrupt number.
When NIRQ is asserted, if the bit “I” of CPSR is 0, the
sequence is:
1. The CPSR is stored in SPSR_irq, the current value
of the Program Counter is loaded in the IRQ link
register (R14_irq) and the Program Counter (R15)
is loaded with 0x18. In the following cycle during
fetch at address 0x1C, the ARM core adjusts
R14_irq, decrementing it by 4.
2. The ARM core enters IRQ mode if it is not already.
3. When the instruction at 0x18 is executed, the Pro-
gram Counter is loaded with the start address of the
default interrupt handler.
4. The previous interrupt priority level is stored onto a
stack. Note that if no interrupt was active, the previ-
ous interrupt priority will be zero.
5. The AIC_IVR register is read causing the IRQ
request to be cancelled and the current interrupt pri-
ority is updated. Any registers that may be used can
be stored onto the stack at this point if required. The