Rainbow Electronics AT75C310 - Manual (Page 17)

AT75C310
17
Read Protocols
The SMC provides two alternative protocols for external
memory read access: standard and early read. The differ-
ence between the two protocols lies in the timing of the
NSOE (read cycle) waveform.
The protocol is selected by the DRP field in the memory
control register (SMC_MCR) and is valid for all memory
devices. Standard read protocol is the default protocol after
reset.
• Standard Read Protocol
Standard read protocol implements a read cycle in which
NSOE and the write strobes are similar. Both are active
during the second half of the clock cycle. The first half of
the clock cycle allows time to ensure completion of the pre-
vious access, as well as the output of address and NCE
before the read cycle begins.
During a standard read protocol external memory access,
NCE is set low and ADDR is valid at the beginning of the
access, whereas NSOE goes low only in the second half of
the master clock cycle to avoid bus conflict. The write
strobes are the same in both protocols. The write strobes
always go low in the second half of the master clock cycle.
• Early Read Protocol
Early read protocol provides more time for a read access
from the memory by asserting NSOE at the beginning of
the clock cycle. In the case of successive read cycles in the
same memory, NSOE remains active continuously. Since a
read cycle normally limits the speed of operation of the
external memory system, early read protocol allows a
faster clock frequency to be used. However, an extra wait
state is required in some cases to avoid contention on the
external bus.
In early read protocol, an early read wait state is automati-
cally inserted when an external write cycle is followed by a
read cycle to allow time for the write cycle to end before the
subsequent read cycle begins. This wait state is generated
in addition to any other programmed wait states (i.e., data
float wait). No wait state is added when a read cycle is fol-
lowed by a write cycle, between consecutive accesses of
the same type or between external and internal memory
accesses. Early read wait states affect the external bus
only. They do not affect internal bus timing.
Write Protocol
During a write cycle, the data becomes valid after the fall-
ing edge of the write strobe signal and remains valid after
the rising edge of the write strobe. The external write strobe
waveform (on the appropriate write strobe pin) is used to
control the output data timing to guarantee this operation.
Thus, it is necessary to avoid excessive loading of the write
strobe pins, which could delay the write signal too long and
cause a contention with a subsequent read cycle in stan-
dard protocol. In early read protocol, the data can remain
valid longer than in standard read protocol due to the addi-
tional wait cycle that follows a write access.
Wait States
The SMC can automatically insert wait states. The different
types of wait states are:
• Standard wait states
• Data float wait states
• External wait states
• Chip select change wait states
• Early read wait states (see “Read Protocols” on page 17
for details)
• Standard wait states
Each chip select can be programmed to insert one or more
wait states during an access on the corresponding device.
This is done by setting the WSE field in the corresponding
SMC_CSR. The number of cycles to insert is programmed
in the NWS field in the same register. The correspondence
between the number of standard wait states programmed
and the number of cycles during which the write strobe
pulse is held low is found in Table 7. For each additional
wait state programmed, an additional cycle is added.
• Data Float Wait State
Some memory devices are slow to release the external
bus. For such devices, it is necessary to add wait states
(data float waits) after a read access before starting a write
access or a read access to a different external memory.
The data float output time (TDF) for each external memory
device is programmed in the TDF field of the SMC_CSR
register for the corresponding chip select. The value (0 - 7
clock cycles) indicates the number of data float waits to be
inserted and represents the time allowed for the data out-
put to go high-impedance after the memory is disabled.
The SMC keeps track of the programmed external data
float time even when making internal accesses, thus ensur-
ing that the external memory system is not accessed while
it is still busy.
Internal memory accesses and consecutive accesses to
the same external memory do not have added data float
wait states.
When data float wait states are being used, the SMC pre-
vents the DMC or external master from accessing the
external data bus.
Table 7. Correspondence Wait States/Number of Cycles
Wait States Cycles
0 1/2
1 1