Rainbow Electronics AT75C310 - Manual (Page 10)

AT75C310
10
Clocking
The AT75C310 uses an external 16 MHz crystal (XCLK)
and two on-chip PLLs to generate the internal clocks. One
PLL generates a 96 MHz clock that is divided down to pro-
duce the ARM clocks and the other produces an 80 MHz
clock used to generate the Oak and Codec interface
clocks.
The ARM core runs at 24 MHz whereas the DSP sub-
systems run at 40 MHz.
Note that there is a common synchronous mode where the
ARM and OAK systems both run from the Oak PLL. This
results in the ARM running at 20 MHz and the Oak at
40 MHz.
A block diagram of the clock circuitry can be seen below in
Figure 2.
Figure 2. AT75C310 Clock Circuitry Diagram
10 pF
XTALOUT
1 M Ω
16 MHz
XTAL
10 pF
XTALIN
Oscillator
16 MHz
100 Ω
10 nF
XREF 96
PLL
100 Ω
10 nF
XREF 80
PLL
.. 6
.. 5
80 MHz
96 MHz
.. 4
Phase
Generator
Phase
Generator
24 MHz
40 MHz
40 MHz
40 MHz
40 MHz
ARM Clock
Core
DSP Subsystem A
Clocks
DSP Subsystem B
Clocks