Xilinx Virtex-5 FPGA ML561 User Manual
Page 99
Virtex-5 FPGA ML561 User Guide
99
UG199 (v1.2.1) June 15, 2009
FPGA #1 Pinout
R
FPGA #1 Test Display Signals
FPGA1_7SEG_0_N AG17
FPGA1_7SEG_6_N AF19
FPGA1_7SEG_1_N AH18
FPGA1_7SEG_DP_N AG21
FPGA1_7SEG_2_N AE18
FPGA1_LED0
AD19
FPGA1_7SEG_3_N AF18
FPGA1_LED1
AE19
FPGA1_7SEG_4_N AG16
FPGA1_LED2
AE17
FPGA1_7SEG_5_N AH17
FPGA1_LED3
AF16
FPGA #1 External Interfaces
FPGA1_LCD_BL_ON M6
FPGA1_LCD_E
M5
FPGA1_LCD_CSB M7
FPGA1_LCD_R_WB N8
FPGA1_LCD_DB0 K6
FPGA1_LCD_RESET_N
L6
FPGA1_LCD_DB1 K7
FPGA1_LCD_RS N7
FPGA1_LCD_DB2 P6
FPGA1_RS232_CTS
R11
FPGA1_LCD_DB3 P7
FPGA1_RS232_RTS G5
FPGA1_LCD_DB4 L5
FPGA1_RS232_RX P9
FPGA1_LCD_DB5 L4
FPGA1_RS232_TX H5
FPGA1_LCD_DB6 P5
FPGA1_TXN0_BK124
B9
FPGA1_LCD_DB7 N5
FPGA1_TXP0_BK124
B10
FPGA1_USB_CTS_N G6
FPGA1_USB_RTS_N G7
FPGA1_USB_DSR_N E6
FPGA1_USB_RX T9
FPGA1_USB_DTR_N E7
FPGA1_USB_SUSPEND
T11
FPGA1_USB_RST_N T10
FPGA1_USB_TX U10
FPGA #1 Voltage Margining Interface
VMARGIN_DN_3V3_N AE22
VMARGIN_UP_3V3_N AE23
VMARGIN_DN_HSTL_N AE13
VMARGIN_UP_HSTL_N AE12
VMARGIN_DN_SSTL18_N AF13
VMARGIN_UP_SSTL18_N AG12
VMARGIN_DN_SSTL2_N AF23
VMARGIN_UP_SSTL2_N AG23
VMARGIN_DN_VCC1V0_N AF20
VMARGIN_UP_VCC1V0_N AF21
VMARGIN_DN_VCC2V5_N AE14
VMARGIN_UP_VCC2V5_N AF14
Table A-1:
FPGA #1 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin