Xilinx Virtex-5 FPGA ML561 User Manual
Page 112
112
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix A: FPGA Pinouts
R
RLDRAM II Memory Interface (cont.)
RLD2_D_BY0_B5
F8
RLD2_DM_BY2_3_N
T9
RLD2_D_BY0_B6
F9
RLD2_DQ_BY0_B0
G13
RLD2_D_BY0_B7
E8
RLD2_DQ_BY0_B1
F13
RLD2_D_BY0_B8
E9
RLD2_DQ_BY0_B2
N9
RLD2_D_BY1_B0
R11
RLD2_DQ_BY0_B3
N10
RLD2_D_BY1_B1
R7
RLD2_DQ_BY0_B4
E13
RLD2_D_BY1_B2
J6
RLD2_DQ_BY0_B5
E12
RLD2_D_BY1_B3
T6
RLD2_DQ_BY0_B6
L9
RLD2_D_BY1_B4
R6
RLD2_DQ_BY0_B7
M10
RLD2_D_BY1_B5
K6
RLD2_DQ_BY0_B8
E11
RLD2_D_BY1_B6
K7
RLD2_DQ_BY1_B0
J10
RLD2_D_BY1_B7
P6
RLD2_DQ_BY1_B1
B12
RLD2_D_BY1_B8
P7
RLD2_DQ_BY1_B2
A13
RLD2_D_BY2_B0
V9
RLD2_DQ_BY1_B3
H9
RLD2_D_BY2_B1
V10
RLD2_DQ_BY1_B4
H10
RLD2_D_BY2_B2
AK6
RLD2_DQ_BY1_B5
C12
RLD2_D_BY2_B3
AK7
RLD2_DQ_BY1_B6
D12
RLD2_D_BY2_B4
U8
RLD2_DQ_BY1_B7
J11
RLD2_D_BY2_B5
V8
RLD2_DQ_BY1_B8
K11
RLD2_D_BY2_B6
AJ6
RLD2_DQ_BY2_B0
E7
RLD2_D_BY2_B7
AJ7
RLD2_DQ_BY2_B1
E6
RLD2_D_BY2_B8
W9
RLD2_DQ_BY2_B2
G7
RLD2_D_BY3_B0
Y8
RLD2_DQ_BY2_B3
G6
RLD2_D_BY3_B1
AD7
RLD2_DQ_BY2_B4
F6
RLD2_D_BY3_B2
AC7
RLD2_DQ_BY2_B5
F5
RLD2_D_BY3_B3
AB5
RLD2_DQ_BY2_B6
J5
RLD2_D_BY3_B4
AA5
RLD2_DQ_BY2_B7
G5
RLD2_D_BY3_B5
AB7
RLD2_DQ_BY2_B8
H5
RLD2_D_BY3_B6
AB6
RLD2_DQ_BY3_B0
L4
RLD2_D_BY3_B7
AC5
RLD2_DQ_BY3_B1
P5
RLD2_D_BY3_B8
AC4
RLD2_DQ_BY3_B2
N5
RLD2_DM_BY0_1_N
G12
RLD2_DQ_BY3_B3
L6
Table A-3:
FPGA #3 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin