Xilinx Virtex-5 FPGA ML561 User Manual
Page 103
Virtex-5 FPGA ML561 User Guide
103
UG199 (v1.2.1) June 15, 2009
FPGA #2 Pinout
R
DDR2 DIMM Wide Interface (cont.)
DDR2_DIMM5_CS0_N
V24
DDR2_DIMM_DQ_BY11_B5
G6
DDR2_DIMM5_CS1_N
W24
DDR2_DIMM_DQ_BY11_B6
T11
DDR2_DIMM5_ODT0
AA9
DDR2_DIMM_DQ_BY11_B7
T10
DDR2_DIMM5_ODT1
AA8
DDR2_DIMM_DQ_BY12_B0
J6
DDR2_DIMM_LB_BK12
F5
DDR2_DIMM_DQ_BY12_B1
T6
DDR2_DIMM_LB_BK12
F6
DDR2_DIMM_DQ_BY12_B2
R6
DDR2_DIMM_LB_BK18
W10
DDR2_DIMM_DQ_BY12_B3
K6
DDR2_DIMM_LB_BK18
Y6
DDR2_DIMM_DQ_BY12_B4
K7
DDR2_DIMM_LB_BK20
E11
DDR2_DIMM_DQ_BY12_B5
P6
DDR2_DIMM_LB_BK20
F11
DDR2_DIMM_DQ_BY12_B6
P7
DDR2_DIMM_DM_BY10
G11
DDR2_DIMM_DQ_BY12_B7
L4
DDR2_DIMM_DM_BY11
R11
DDR2_DIMM_DQ_BY13_B0
AD7
DDR2_DIMM_DM_BY12
G5
DDR2_DIMM_DQ_BY13_B1
AC7
DDR2_DIMM_DM_BY13
Y11
DDR2_DIMM_DQ_BY13_B2
AB5
DDR2_DIMM_DM_BY14
AH7
DDR2_DIMM_DQ_BY13_B3
AA5
DDR2_DIMM_DM_BY15
W11
DDR2_DIMM_DQ_BY13_B4
AB7
DDR2_DIMM_DM_BY8
M8
DDR2_DIMM_DQ_BY13_B5
AB6
DDR2_DIMM_DM_BY9
G12
DDR2_DIMM_DQ_BY13_B6
AC5
DDR2_DIMM_DM_CB8_15
H5
DDR2_DIMM_DQ_BY13_B7
AC4
DDR2_DIMM_DQ_BY10_B0
H8
DDR2_DIMM_DQ_BY14_B0
V9
DDR2_DIMM_DQ_BY10_B1
G8
DDR2_DIMM_DQ_BY14_B1
V10
DDR2_DIMM_DQ_BY10_B2
G10
DDR2_DIMM_DQ_BY14_B2
AK6
DDR2_DIMM_DQ_BY10_B3
F10
DDR2_DIMM_DQ_BY14_B3
AK7
DDR2_DIMM_DQ_BY10_B4
F8
DDR2_DIMM_DQ_BY14_B4
U8
DDR2_DIMM_DQ_BY10_B5
F9
DDR2_DIMM_DQ_BY14_B5
V8
DDR2_DIMM_DQ_BY10_B6
E8
DDR2_DIMM_DQ_BY14_B6
AJ6
DDR2_DIMM_DQ_BY10_B7
E9
DDR2_DIMM_DQ_BY14_B7
AJ7
DDR2_DIMM_DQ_BY11_B0
E7
DDR2_DIMM_DQ_BY15_B0
W6
DDR2_DIMM_DQ_BY11_B1
E6
DDR2_DIMM_DQ_BY15_B1
AE6
DDR2_DIMM_DQ_BY11_B2
U10
DDR2_DIMM_DQ_BY15_B2
AD6
DDR2_DIMM_DQ_BY11_B3
T9
DDR2_DIMM_DQ_BY15_B3
Y7
DDR2_DIMM_DQ_BY11_B4
G7
DDR2_DIMM_DQ_BY15_B4
AA6
Table A-2:
FPGA #2 Pinout (Continued)
Signal Name
Pin
Signal Name
Pin