Xilinx Virtex-5 FPGA ML561 - Manual (Page 114)

114 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix A: FPGA Pinouts R
FPGA #3 Test and Debug Signals (cont.)
FPGA3_TEST_HDR_BY1_B4 AC24 FPGA3_TEST_HDR_BY1_B6 AE26
FPGA3_TEST_HDR_BY1_B5 AC25 FPGA3_TEST_HDR_BY1_B7 AE27
FPGA #3 Test Display Signals
FPGA3_7SEG_0_N AG17 FPGA3_7SEG_6_N AF19
FPGA3_7SEG_1_N AH18 FPGA3_7SEG_DP_N AG21
FPGA3_7SEG_2_N AE18 FPGA3_LED0 AD19
FPGA3_7SEG_3_N AF18 FPGA3_LED1 AE19
FPGA3_7SEG_4_N AG16 FPGA3_LED2 AE17
FPGA3_7SEG_5_N AH17 FPGA3_LED3 AF16
FPGA #3 External Interfaces
FPGA3_RS232_CTS G15 FPGA3_USB_DTR_N H13
FPGA3_RS232_RTS L18 FPGA3_USB_RST_N L19
FPGA3_RS232_RX H18 FPGA3_USB_RTS_N H15
FPGA3_RS232_TX K17 FPGA3_USB_RX J20
FPGA3_USB_CTS_N H14 FPGA3_USB_SUSPEND K19
FPGA3_USB_DSR_N J14 FPGA3_USB_TX J21
FPGA #3 System ACE Control Signals
SYSACE_CTRL0 H12 SYSACE_MPA5 K22
SYSACE_CTRL1 G23 SYSACE_MPA6 J12
SYSACE_CTRL2 H23 SYSACE_MPD0 L21
SYSACE_CTRL3 K13 SYSACE_MPD1 L20
SYSACE_CTRL4 K12 SYSACE_MPD2 L15
SYSACE_MPA0 G22 SYSACE_MPD3 L16
SYSACE_MPA1 H22 SYSACE_MPD4 J22
SYSACE_MPA2 L14 SYSACE_MPD5 K21
SYSACE_MPA3 K14 SYSACE_MPD6 K16
SYSACE_MPA4 K23 SYSACE_MPD7 J15
Table A-3: FPGA #3 Pinout (Continued)
Signal Name Pin Signal Name Pin