Xilinx Virtex-5 FPGA ML561 - Manual (Page 63)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 63
UG199 (v1.2.1) June 15, 2009
Signal Integrity Correlation Results R
Figure 7-8: DDR2 Component Write Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
-200.0 200.0 600.0
Time (ps)
Voltage (mV)
1000.0 1400.0 1800.0
-200.0
0.000
200.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
1600.0
1800.0
Probe 1:U12.D3 (at die)
UG199_c7_08_071007
♦
333 MHz, Slow, PRBS6, 84.5% UI
♦
Cursor 1: 1.1007V, 123.7 ps
♦
Cursor 2: 1.0253V, 1.3921 ns
♦
Delta Voltage = 75.4 mV, Delta Time = 1.2684 ns (84.5% UI)
Figure 7-9: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
65.000 75.000 85.000 95.000 105.000
UG199_c7_09_071007
-200.0
Time (ns)
0.000
200.0
400.0
600.0
Voltage (mV)
800.0
1000.0
1200.0
1400.0
1600.0
1800.0
Probe 1:U12.D3 (at die)