Xilinx Virtex-5 FPGA ML561 - Manual (Page 102)

102 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix A: FPGA Pinouts R
DDR2 DIMM Deep Interface (cont.)
DDR2_DIMM_DQ_BY4_B4 V34 DDR2_DIMM_DQ_BY7_B7 Y32
DDR2_DIMM_DQ_BY4_B5 W34 DDR2_DIMM_DQ_CB0_7_B0 D34
DDR2_DIMM_DQ_BY4_B6 V33 DDR2_DIMM_DQ_CB0_7_B1 C34
DDR2_DIMM_DQ_BY4_B7 V32 DDR2_DIMM_DQ_CB0_7_B2 D32
DDR2_DIMM_DQ_BY5_B0 AP32 DDR2_DIMM_DQ_CB0_7_B3 C32
DDR2_DIMM_DQ_BY5_B1 AN32 DDR2_DIMM_DQ_CB0_7_B4 C33
DDR2_DIMM_DQ_BY5_B2 AN33 DDR2_DIMM_DQ_CB0_7_B5 B33
DDR2_DIMM_DQ_BY5_B3 AN34 DDR2_DIMM_DQ_CB0_7_B6 A33
DDR2_DIMM_DQ_BY5_B4 AM32 DDR2_DIMM_DQ_CB0_7_B7 B32
DDR2_DIMM_DQ_BY5_B5 AM33 DDR2_DIMM_DQS_BY0_L_N N30
DDR2_DIMM_DQ_BY5_B6 AL33 DDR2_DIMM_DQS_BY0_L_P M31
DDR2_DIMM_DQ_BY5_B7 AL34 DDR2_DIMM_DQS_BY1_L_N P30
DDR2_DIMM_DQ_BY6_B0 U31 DDR2_DIMM_DQS_BY1_L_P P31
DDR2_DIMM_DQ_BY6_B1 U32 DDR2_DIMM_DQS_BY2_L_N L31
DDR2_DIMM_DQ_BY6_B2 T34 DDR2_DIMM_DQS_BY2_L_P K31
DDR2_DIMM_DQ_BY6_B3 U33 DDR2_DIMM_DQS_BY3_L_N J34
DDR2_DIMM_DQ_BY6_B4 R32 DDR2_DIMM_DQS_BY3_L_P H34
DDR2_DIMM_DQ_BY6_B5 R33 DDR2_DIMM_DQS_BY4_L_N AE34
DDR2_DIMM_DQ_BY6_B6 R34 DDR2_DIMM_DQS_BY4_L_P AF34
DDR2_DIMM_DQ_BY6_B7 T33 DDR2_DIMM_DQS_BY5_L_N AE32
DDR2_DIMM_DQ_BY7_B0 AF33 DDR2_DIMM_DQS_BY5_L_P AD32
DDR2_DIMM_DQ_BY7_B1 AB33 DDR2_DIMM_DQS_BY6_L_N K32
DDR2_DIMM_DQ_BY7_B2 AC33 DDR2_DIMM_DQS_BY6_L_P K33
DDR2_DIMM_DQ_BY7_B3 AB32 DDR2_DIMM_DQS_BY7_L_N AJ34
DDR2_DIMM_DQ_BY7_B4 AC32 DDR2_DIMM_DQS_BY7_L_P AH34
DDR2_DIMM_DQ_BY7_B5 AD34 DDR2_DIMM_DQS_CB0_7_L_N K34
DDR2_DIMM_DQ_BY7_B6 AC34 DDR2_DIMM_DQS_CB0_7_L_P L34
DDR2 DIMM Wide Interface
DDR2_DIMM5_CK0_N AM13 DDR2_DIMM5_CK2_N AP14
DDR2_DIMM5_CK0_P AN13 DDR2_DIMM5_CK2_P AN14
DDR2_DIMM5_CK1_N AA10 DDR2_DIMM5_CKE0 AC10
DDR2_DIMM5_CK1_P AB10 DDR2_DIMM5_CKE1 AM11
Table A-2: FPGA #2 Pinout (Continued)
Signal Name Pin Signal Name Pin