Memories, Ddr400 sdram components, Ddr2 dimm – Xilinx Virtex-5 FPGA ML561 User Manual
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Virtex-5 FPGA ML561 User Guide
19
UG199 (v1.2.1) June 15, 2009
Hardware Overview
R
Memories
lists the types of memories that the ML561 board supports.
When a larger data/strobe ratio is implemented, for example, a x36 QDRII device, the
smaller configurations can also be demonstrated by programming the FPGA for a smaller
data width, such as a 9:1 data/strobe ratio for the QDRII device.
DDR400 SDRAM Components
The Virtex-5 FPGA ML561 Development Board has two 200 MHz Micron
MT46V32M16BN-5B (16-bit) DDR400 SDRAM components that provide a 32-bit interface.
Each 16-bit device is packaged in a 60-ball FBGA package, with a common address and
control bus and separate clocks and DQS/DQ signals.
DDR2 DIMM
The Virtex-5 FPGA ML561 Development Board contains five PC-5300 240-pin DIMM
sockets for a maximum data width of 144 bits or a maximum depth of four DIMMs. The
sockets are arranged in a row leading away from the FPGA so they can share common
address and control signals. DIMM1 through DIMM4 share DQ/DQS signals to form a
deep 72-bit memory interface, while DIMM5 has separate DQ/DQS signals.
For the deep DDR2 interface, the sockets are to be populated starting at socket DIMM4.
illustrates how the sockets should be populated based on the interface wanted.
Populating the DIMMs in this order is necessary due to the placement of the termination
on the signals being shared. More detail on termination is given in
.
Table 3-1:
Summary of ML561 Memory Interfaces
Memory Type
Maximum Speed
Data Rate
Data Width
I/O Standard
Data/Strobe
Ratios
DDR400 SDRAM
200 MHz
400 Mbps
32
SSTL2
8:1
DDR2 DIMM
333 MHz
667 Mbps
144
SSTL18
8:1
DDR2 SDRAM
333 MHz
667 Mbps
32
SSTL18
8:1
QDRII SRAM
300 MHz
1.2 Gbps
72
HSTL18
18:1, 36:1
RLDRAM II
300 MHz
600 Mbps
36
HSTL18
9:1, 18:1
Table 3-2:
Populating DDR2 DIMM Sockets
DIMM Interface
DIMM Sockets
Populated
Interface Width
One Deep
5 or 4
72-bit
Two Deep
4 and 3
72-bit
Three Deep
4, 3, and 2
72-bit
Four Deep
4, 3, 2, and 1
72-bit
Two Wide
5 and 4
144-bit