Test setup – Xilinx Virtex-5 FPGA ML561 User Manual
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Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Chapter 7: ML561 Hardware-Simulation Correlation
R
illustrated here for these signals can be easily adopted to perform SI analysis for any other
memory interface signal on the ML561 board.
This chapter presents the SI results for the following six data bit signals:
•
DDR2 component DQ bit (DDR2_DQ_BY2_B3) for write operations
•
DDR2 component DQ bit (DDR2_DQ_BY2_B3) for read operations
•
DDR2 DIMM DQ bit (DDR2_DIMM_DQ_BY2_B3) for write operations
•
DDR2 DIMM DQ bit (DDR2_DIMM_DQ_BY2_B3) for read operations
•
QDRII D bit (QDR2_D_BY0_B5) for write operations
•
QDRII Q bit (QDR2_Q_BY0_B5) for read operations
Test Setup
Hardware measurements were performed for the six specific signal nets, and then signal
integrity (SI) simulations were performed for correlation and extrapolation. The test setup
consisted of the following hardware equipment, simulation software tools, the stimulus
test pattern, and test criteria for determining the quality of signals. The test bench is
designed so that the test pattern is applied only to the signal under test, and all other data
bits to the same memory interface are kept in a quiet Low state. This setup ensures that the
hardware measurement is not altered due to any simultaneous switching output (SSO)
effect.
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Hardware measurement equipment
♦
Agilent DSO80604B 6 GHz oscilloscope
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Agilent 1131A 3.5 GHz Infiniimax probe amplifier
♦
Agilent E2675A (Differential browser) or E2677A (Differential solder-in probe) or
N5425A (ZIF probe)
♦
v B2 board: S/N 103
♦
SRS Model CG635 Synthesized Clock Generator for low jitter clock source
•
Simulation software
♦
Mentor Graphics HyperLynx EXT, Version 7.5 with LineSim and BoardSim
features
♦
Xilinx Virtex-5 FPGA IBIS package file: ff1136_5vlx50t.pkg, Rev 1.0 dated
June 12, 2006
♦
ML561, Rev B layout file: ML561_B_041706.hyp
♦
Micron DDR2-667 IBIS model for output and ODT input
♦
Micron PC2-5300 RDIMM IBIS model
♦
Molex DDR2 DIMM socket specification (P/N 087705-1041)
♦
Samsung QDRII HSTL 1.8V IBIS model
♦
ity of ISE software suite to create customized IBIS model of the
FPGA1 (U7) and FPGA3 (U34) devices on the ML561 board: Model files
ml561_fpga1_u7.ibs
User-Specific FPGA IBIS Model,” page 93
for steps on how to create a customized
IBIS model of Virtex-5 FPGA for your design.)
•
Stimulus
Pseudo Random Bit Stream (PRBS) is accepted as the most effective test pattern to
measure the quality of data signals because, unlike the periodic signals like clock and