Texas Instruments TMS320C6454 User Manual
Product preview
Table of contents
Document Outline
- 1 TMS320C6454 Fixed-Point Digital Signal Processor
- Table of Contents
- 2 Device Overview
- 3 Device Configuration
- 3.1 Device Configuration at Device Reset
- 3.2 Peripheral Configuration at Device Reset
- 3.3 Peripheral Selection After Device Reset
- 3.4 Device State Control Registers
- 3.4.1 Peripheral Lock Register Description
- 3.4.2 Peripheral Configuration Register 0 Description
- 3.4.3 Peripheral Configuration Register 1 Description
- 3.4.4 Peripheral Status Registers Description
- 3.4.5 EMAC Configuration Register (EMACCFG) Description
- 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description
- 3.5 Device Status Register Description
- 3.6 JTAG ID (JTAGID) Register Description
- 3.7 Pullup/Pulldown Resistors
- 3.8 Configuration Examples
- 4 System Interconnect
- 5 C64x+ Megamodule
- 6 Device Operating Conditions
- 7 C64x+ Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 Enhanced Direct Memory Access (EDMA3) Controller
- 7.5 Interrupts
- 7.6 Reset Controller
- 7.7 PLL1 and PLL1 Controller
- 7.8 PLL2 and PLL2 Controller
- 7.9 DDR2 Memory Controller
- 7.10 External Memory Interface A (EMIFA)
- 7.11 I2C Peripheral
- 7.12 Host-Port Interface (HPI) Peripheral
- 7.13 Multichannel Buffered Serial Port (McBSP)
- 7.14 Ethernet MAC (EMAC)
- 7.15 Timers
- 7.16 Peripheral Component Interconnect (PCI)
- 7.17 General-Purpose Input/Output (GPIO)
- 7.18 IEEE 1149.1 JTAG
- 8 Mechanical Data
- Revision History