3 emifa electrical data/timing, Product preview – Texas Instruments TMS320C6454 User Manual
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PRODUCT PREVIEW
7.10.3 EMIFA Electrical Data/Timing
AECLKIN
2
3
4
4
5
1
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 7-42. Timing Requirements for AECLKIN for EMIFA
(1) (2)
(see
)
-720
-850
NO.
UNIT
-1000
MIN
MAX
1
t
c(EKI)
Cycle time, AECLKIN
6
(3)
40
ns
2
t
w(EKIH)
Pulse duration, AECLKIN high
2.7
ns
3
t
w(EKIL)
Pulse duration, AECLKIN low
2.7
ns
4
t
t(EKI)
Transition time, AECLKIN
2
ns
5
t
J(EKI)
Period Jitter, AECLKIN
0.02E
(4)
ns
(1)
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
(2)
E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
(3)
Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times
are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.
(4)
This timing only applies when AECLKIN is used for EMIFA.
Figure 7-31. AECLKIN Timing for EMIFA
C64x+ Peripheral Information and Electrical Specifications
151