Texas Instruments TMS320C6454 - Manual (Page 121)

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PRODUCT PREVIEW
CLKIN1
PCLK
RESET
RESETSTAT
SYSREFCLK (PLL1C)
Z Group
POR
SYSCLK3
SYSCLK4
SYSCLK5
AECLKOUT (Internal)
Boot and Device
Configuration Pins
Low Group
High Group
CLKIN2
Internal Reset PLL2C
SYSREFCLK (PLL2C)
SYSCLK1 (PLL2C)
SYSCLK2
5
9
7
8
Undefined
Undefined Low
High-Z
Undefined
High
PLL2 Unlocked PLL2 Locked (A)
PLL2 Unlocked Clock Valid
Undefined
Undefined
Undefined Clock Valid (B)
Power Supplies Ramping Power Supplies Stable
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
A. SYSREFCLK of the PLL2 controller runs at CLKIN2 ×10.
B. SYSCLK1 of PLL2 controller runs at SYSREFCLK/2 (default).
C. Power supplies, CLKIN1, CLKIN2 (if used), and PCLK (if used) must be stable before the start of t
w(POR)
.
Figure 7-8. Power-Up Timing
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