Texas Instruments TMS320C6454 - Manual (Page 146)

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PRODUCT PREVIEW
7.8.4 PLL2 Controller Input Clock Electrical Data/Timing
CLKIN2
2
3
4
4
5 1
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 7-39. Timing Requirements for CLKIN2
(1) (2) (3)
(see Figure 7-30 )
-720
-850
NO. UNIT
-1000
MIN MAX
1 t
c(CLKIN2)
Cycle time, CLKIN2 37.5 80 ns
2 t
w(CLKIN2H)
Pulse duration, CLKIN2 high 0.4C ns
3 t
w(CLKIN2L)
Pulse duration, CLKIN2 low 0.4C ns
4 t
t(CLKIN2)
Transition time, CLKIN2 1.2 ns
5 t
J(CLKIN2)
Period jitter (peak-to-peak), CLKIN2 100 ps
(1) The reference points for the rise and fall transitions are measured at 3.3 V V
IL
MAX and V
IH
MIN.
(2) C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.
(3) If EMAC is enabled with RGMII or GMII, CLKIN2 cycle time must be 40 ns (25 MHz).
Figure 7-30. CLKIN2 Timing
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