Texas Instruments TMS320C6454 - Manual (Page 75)

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PRODUCT PREVIEW
Megamodule M
CFG SCR
S
M
McBSPs S
Timers S
HPI S
PCI S
S
Bridge
7
GPIO S
EMAC/MDIO
M Data SCR S
S
I2C S S
PLL
Controllers (A)
S
S
Device
Configuration
Registers (A)
EDMA3 TC0 S
EDMA3 TC1 S
S EDMA3 TC2
S
EDMA3 CC S S
EDMA3 TC3 S
M
32
(SYSCLK3)
MUX
32
(SYSCLK2)
32
(SYSCLK2)
32 (SYSCLK2)
32
(SYSCLK3)
32 (SYSCLK2)
32 (SYSCLK2)
32-bit
(SYSCLK2)
Configuration Bus
Data Bus
MUX
32
(SYSCLK2)
32
(SYSCLK2)
32
(SYSCLK2)
32
(SYSCLK2)
A. Only accessible by the C64x+ Megamodule.
B. All clocks in this figure are generated by the PLL1 controller.
32
(SYSCLK3)
32
(SYSCLK3)
32
(SYSCLK3)
32
(SYSCLK3)
32
(SYSCLK3)
32
(SYSCLK3)
32
(SYSCLK3)
32
(SYSCLK3)
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Figure 4-2. C64x+ Megamodule - SCR Connection
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