Texas Instruments TMS320C6454 - Manual (Page 190)

www.ti.com
PRODUCT PREVIEW
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Interface Mode Clocking
The on-chip PLL2 and PLL2 Controller generate all the clocks to the EMAC module. When enabled, the
input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency. For more information, see
Section 7.8 , PLL2 and PLL2 Controller.
The EMAC uses SYSCLK1 of the PLL2 Controller to generate the necessary clocks for the GMII and
RGMII modes. When these modes are used, the frequency of CLKIN2 must be 25 MHz. Also, divider D1
should be programmed to
÷
2 mode [default] when using the GMII mode and to
÷
5 mode when using the
RGMII mode. Divider D1 is software programmable and, if necessary, must be programmed after device
reset to
÷
5 when the RGMII mode of the EMAC is used.
190 C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback