Block diagram, Handling the board, Block diagram –4 – Altera Stratix III Development Board User Manual
Page 8: Handling the board –4
1–4
Chapter 1: Overview
Handling the Board
Stratix III 3SL150 Development Board
May 2013
Altera Corporation
Reference Manual
Block Diagram
shows the functional block diagram of the Stratix III development board.
Handling the Board
When handling the board, it is important to observe the following precaution:
c
Static Discharge Precaution: Without proper anti-static handling, the board can be
damaged. Therefore, use anti-static handling precautions when touching the board.
Figure 1–1. Stratix III Development Board Block Diagram
1.5-V HSTL
Statix III
EP3SL1501152
EP3SL340H1152
125-MHz
XTAL
MAX II
Device (x16)
2.5-V CMOS
1.8-V CMOS
Power
Measure/
Display
72-Mbit QDRII/+
18/18
CMOS + LVDS
4-MB SSRAM
(x32)
64-MB Flash
(x16)
1-GByte DDR2
(x72)
USB
2.0
1.8-V SSTL
50-MHz
XTAL
1.8-V CMOS
Quad 7-Seg/
User LEDs,
Buttons,
Switches
SMA Input
1.8-V SSTL
SMA Output
10/100/1000
Ethernet
CMOS + LVDS
2.5-V CMOS
RJ45
Jack
Graphics Display
Header
14-Pin LCD
Header
16-MB
DDR2
(x8)
16-MB
DDR2
(x8)
HSMC Port B
HSMC Port A
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)