Altera Stratix III Development Board - Manual (Page 14)

2–6 Chapter 2: Board Components
Featured FPGA (U22)
Stratix III 3SL150 Development Board May 2013 Altera Corporation
Reference Manual
Device Support
Although the target FPGA for the Stratix III development board is the EP3SL150
device, which is the first device in the 65 nm Stratix III FPGA device family, the board
is also designed to migrate to the Stratix III EP3SL340H1152 device.
The following list shows the main power rails for the target device:
■ 0.9-V/1.1-V V
CCL
■ 1.1-V V
CC
■ 2.5-V V
CCPT
■ 1.8-V/2.5-V/3.0-V V
CCPGM
■ 2.5-V/3.0-V V
CCPD
■ 2.5-V V
CCA_PLL
■ 2.5-V V
CC_CLKIN
■ 2.5-V V
CCBAT
■ 1.2-V to 3.3-V V
CCIO
The board’s target device, the EP3SL150F1152C2, comprises the following:
■ 57,000 adaptive logic modules (ALMs)
■ 142,000 LEs
■ 1,775 KBytes of RAM
■ 736 user I/O
■ 8 PLLs
■ 16 global clocks
■ 384 18 × 18 multipliers in finite impulse response (FIR) mode
The board is designed to migrate to the EP3SL340H1152C3 device, which provides the
following features in the H1152 package:
■ 135,000 ALMs
■ 338,000 LEs
■ 4,225 KBytes of RAM
■ 736 user I/O
■ 8 PLLs
■ 16 global clocks
■ 576 18 × 18 multipliers in FIR mode
I/O Resources
This section lists specific I/O resources available with the EP3SL150F1152 device,
which is from the L family of Stratix III devices.