Altera Stratix III Development Board - Manual (Page 52)

2–44 Chapter 2: Board Components
Components and Interfaces
Stratix III 3SL150 Development Board May 2013 Altera Corporation
Reference Manual
J18 pin 72 LVDS RX or CMOS I/O bit 4 HSMA_RX_P4 LVDS or 2.V5 AJ2
J18 pin 73 LVDS TX or CMOS I/O bit 4 HSMA_TX_N4 LVDS or 2.5 V AF5
J18 pin 74 LVDS RX or CMOS I/O bit 4 HSMA_RX_N4 LVDS or 2.5 V AK1
J18 pin 77 LVDS TX or CMOS I/O bit 5 HSMA_TX_P5 LVDS or 2.5 V AD7
J18 pin 78 LVDS RX or CMOS I/O bit 5 HSMA_RX_P5 LVDS or 2.5 V AH2
J18 pin 79 LVDS TX or CMOS I/O bit 5 HSMA_TX_N5 LVDS or 2.5 V AD6
J18 pin 80 LVDS RX or CMOS I/O bit 5 HSMA_RX_N5 LVDS or 2.5 V AJ1
J18 pin 83 LVDS TX or CMOS I/O bit 6 HSMA_TX_P6 LVDS or 2.5 V AE6
J18 pin 84 LVDS RX or CMOS I/O bit 6 HSMA_RX_P6 LVDS or 2.5 V AF4
J18 pin 85 LVDS TX or CMOS I/O bit 6 HSMA_TX_N6 LVDS or 2.5 V AE5
J18 pin 86 LVDS RX or CMOS I/O bit 6 HSMA_RX_N6 LVDS or 2.5 V AF3
J18 pin 89 LVDS TX or CMOS I/O bit 7 HSMA_TX_P7 LVDS or 2.5 V AD4
J18 pin 90 LVDS RX or CMOS I/O bit 7 HSMA_RX_P7 LVDS or 2.5 V AG1
J18 pin 91 LVDS TX or CMOS I/O bit 7 HSMA_TX_N7 LVDS or 2.5 V AD3
J18 pin 92 LVDS RX or CMOS I/O bit 7 HSMA_RX_N7 LVDS or 2.5 V AH1
J18 pin 95 LVDS or CMOS clock out HSMA_CLK_OUT_P1 LVDS or 2.5 V V10
J18 pin 96 LVDS or CMOS clock in HSMA_CLK_IN_P1 LVDS or 2.5 V Y4
J18 pin 97 LVDS or CMOS clock out HSMA_CLK_OUT_N1 LVDS or 2.5 V W9
J18 pin 98 LVDS or CMOS clock in HSMA_CLK_IN_N1 LVDS or 2.5 V W3
J18 pin 101 LVDS TX or CMOS I/O bit 8 HSMA_TX_P8 LVDS or 2.5 V AC6
J18 pin 102 LVDS RX or CMOS I/O bit 8 HSMA_RX_P8 LVDS or 2.5 V AF2
J18 pin 103 LVDS TX or CMOS I/O bit 8 HSMA_TX_N8 LVDS or 2.5 V AC5
J18 pin 104 LVDS RX or CMOS I/O bit 8 HSMA_RX_N8 LVDS or 2.5 V AF1
J18 pin 107 LVDS TX or CMOS I/O bit 9 HSMA_TX_P9 LVDS or 2.5 V AB6
J18 pin 108 LVDS RX or CMOS I/O bit 9 HSMA_RX_P9 LVDS or 2.5 V AE2
J18 pin 109 LVDS TX or CMOS I/O bit 9 HSMA_TX_N9 LVDS or 2.5 V AB5
J18 pin 110 LVDS RX or CMOS I/O bit 9 HSMA_RX_N9 LVDS or 2.5 V AE1
J18 pin 113 LVDS TX or CMOS I/O bit 10 HSMA_TX_P10 LVDS or 2.5 V AB8
J18 pin 114 LVDS RX or CMOS I/O bit 10 HSMA_RX_P10 LVDS or 2.5 V AE4
J18 pin 115 LVDS TX or CMOS I/O bit 10 HSMA_TX_N10 LVDS or 2.5 V AC7
J18 pin 116 LVDS RX or CMOS I/O bit 10 HSMA_RX_N10 LVDS or 2.5 V AE3
J18 pin 119 LVDS TX or CMOS I/O bit 11 HSMA_TX_P11 LVDS or 2.5 V Y6
J18 pin 120 LVDS RX or CMOS I/O bit 11 HSMA_RX_P11 LVDS or 2.5 V AC2
J18 pin 121 LVDS TX or CMOS I/O bit 11 HSMA_TX_N11 LVDS or 2.5 V Y5
J18 pin 122 LVDS RX or CMOS I/O bit 11 HSMA_RX_N11 LVDS or 2.5 V AD1
J18 pin 125 LVDS TX or CMOS I/O bit 12 HSMA_TX_P12 LVDS or 2.5 V AA7
J18 pin 126 LVDS RX or CMOS I/O bit 12 HSMA_RX_P12 LVDS or 2.5 V AB2
J18 pin 127 LVDS TX or CMOS I/O bit 12 HSMA_TX_N12 LVDS or 2.5 V AA6
J18 pin 128 LVDS RX or CMOS I/O bit 12 HSMA_RX_N12 LVDS or 2.5 V AC1
Table 2–41. HSMC Port A Interface Signal Name, Description, and Type (Part 2 of 3)
Board
Reference
Description
Schematic
Signal Name
I/O
Standard
Stratix III
Pin Number