Table 2–33 – Altera Stratix III Development Board User Manual
Page 42
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2–34
Chapter 2: Board Components
General User Interfaces
Stratix III 3SL150 Development Board
May 2013
Altera Corporation
Reference Manual
shows pin definitions, and is an excerpt from the Lumex data sheet.
f
For more information such as timing, character maps, interface guidelines, and
related documentation, visi
shows a functional block diagram of the Lumex LCD display device.
1
The particular model used does not have a backlight and the LCD drive pin is not
connected.
Table 2–33. Character LCD Display Pin Definitions
Pin Number
Symbol
Level
Function
1
V
DD
—
Power supply
5 V
2
V
SS
—
GND (0V)
3
V
0
—
For LCD drive
4
RS
H/L
Register select signal
H: Data input
L: Instruction input
5
R/W
H/L
H: Data read (module to MPU)
L: Data write (MPU to module)
6
E
H, H to L
Enable
7~14
DB0~DB7
H/L
Data bus, software selectable 4- or 8-bit mode
Figure 2–10. LCD Display Block Diagram
Block Diagram
16 X 2, 1/16 Duty, 1/5 Bias
E
SEC 80
COM 16
R/W
RS
DB[7:0]
LCD
Panel
LCD
Controller
LSI
and
Driver
LED Backlight
A
K
V
DD
V
SS
V
O
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
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- ALTDQ_DQS2 (100 pages)
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- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
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- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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- DCFIFO (28 pages)