Altera Arria V GX Starter Board User Manual
Page 59
Chapter 2: Board Components
2–51
Power Supply
November 2013
Altera Corporation
Arria V GX Starter Board
Reference Manual
lists the power measurement ADC component reference and
manufacturing information.
3
A5_VCCIO_VCCPD_VCCPGM
2.5
VCCPD
I/O pre-drivers
2.5
VCCPGM
Configuration I/O
2.5
VCCIO_3A,
VCCIO_3B,
VCCIO_3C,
VCCIO_3D,
VCCIO_4A,
VCCIO_4B,
VCCIO_4C,
VCCIO_4D,
VCCIO_7A,
VCCIO_7B,
VCCIO_7C,
VCCIO_7D,
VCCIO_8D
VCC I/O banks 3, 4, 7 and 8D
4
A5_VCCAUX_VCCA_FPLL
2.5
VCCA_FPLL
PLL analog power
2.5
VCC_AUX
Auxiliary
5
A5_VCCA_GXB
2.5
VCCA_GXB
XCVR transmit driver, receiver, CDR
6
A5_VCCH_GXB
1.5
VCCH_GXB
XCVR block level transmit buffers
7
A5_VCCD_FPLL_VCCBAT
1.5
VCCD_FPLL
PLL digital power
1.5
VCCBAT
Battery power
Table 2–50. Power Measurement Rails (Part 2 of 2)
Channel
Schematic Signal Name
Voltage (V)
Device Pin
Description
Table 2–51. Power Measurement ADC Component Reference and Manufacturing Information
Board Reference
Description
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U40
8-channel differential 24-bit ADC
Linear Technology
LTC2418CGN#PBF
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)