Altera Arria V GX Starter Board - Manual (Page 38)

2–30 Chapter 2: Board Components
Components and Interfaces
Arria V GX Starter Board November 2013 Altera Corporation
Reference Manual
10/100/1000 Ethernet
The starter board supports 10/100/1000 base-T Ethernet using an external Marvell
88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The
PHY-to-MAC interface employs a RGMII interface to the Arria V GX. The MAC
function must be provided in the FPGA for typical networking applications.
The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25-MHz
reference clock driven from a dedicated oscillator. The PHY interfaces to a Wurth
Elektronik model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Table 2–32 lists the Ethernet PHY interface pin assignments.
A30 PCIE_TX_CN3 AC31 1.5-V PCML Transmit bus
A35 PCIE_TX_CP4 W32 1.5-V PCML Transmit bus
A36 PCIE_TX_CN4 W31 1.5-V PCML Transmit bus
A39 PCIE_TX_CP5 U32 1.5-V PCML Transmit bus
A40 PCIE_TX_CN5 U31 1.5-V PCML Transmit bus
A43 PCIE_TX_CP6 R32 1.5-V PCML Transmit bus
A44 PCIE_TX_CN6 R31 1.5-V PCML Transmit bus
A47 PCIE_TX_CP7 N32 1.5-V PCML Transmit bus
A48 PCIE_TX_CN7 N31 1.5-V PCML Transmit bus
B11 PCIE_WAKEN E14 2.5-V Wake signal
Table 2–31. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J1)
Schematic Signal Name
Arria V GX
Pin Number
I/O Standard Description
Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
10/100/1000 Mbps
Ethernet MAC
Marvell 88E1111
PHY
Device
Transformer RJ45
RGMII Interface
TXD[3:0]
RXD[3:0]
CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board
Reference (U20)
Schematic Signal Name
Arria V GX
Pin Number
I/O Standard Description
23 ENET_INTN AG11 2.5-V CMOS Management bus interrupt
25 ENET_MDC AJ11 2.5-V CMOS Management bus data clock
24 ENET_MDIO AH11 2.5-V CMOS Management bus data
28 ENET_RESETN AL11 2.5-V CMOS Device reset
2 ENET_RX_CLK AL4 2.5-V CMOS RGMII receive clock