Altera Arria V GX Starter Board - Manual (Page 49)

Chapter 2: Board Components 2–41
Memory
November 2013 Altera Corporation Arria V GX Starter Board
Reference Manual
C7 DDR3_DQS_P1 F23
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 1
B7 DDR3_DQS_N1 G23
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 1
K1 DDR3_ODT H27 1.5-V SSTL Class I On-die termination enable
J3 DDR3_RASN B30 1.5-V SSTL Class I Row address select
T2 DDR3_RESETN K25 1.5-V SSTL Class I Reset
L3 DDR3_WEN F29 1.5-V SSTL Class I Write enable
L8 DDR3_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U10)
N3 DDR3_A0 D26 1.5-V SSTL Class I Address bus
P7 DDR3_A1 E27 1.5-V SSTL Class I Address bus
P3 DDR3_A2 A27 1.5-V SSTL Class I Address bus
N2 DDR3_A3 B27 1.5-V SSTL Class I Address bus
P8 DDR3_A4 G26 1.5-V SSTL Class I Address bus
P2 DDR3_A5 H26 1.5-V SSTL Class I Address bus
R8 DDR3_A6 K27 1.5-V SSTL Class I Address bus
R2 DDR3_A7 L27 1.5-V SSTL Class I Address bus
T8 DDR3_A8 D27 1.5-V SSTL Class I Address bus
R3 DDR3_A9 C28 1.5-V SSTL Class I Address bus
L7 DDR3_A10 C29 1.5-V SSTL Class I Address bus
R7 DDR3_A11 D28 1.5-V SSTL Class I Address bus
N7 DDR3_A12 G27 1.5-V SSTL Class I Address bus
T3 DDR3_A13 G28 1.5-V SSTL Class I Address bus
M2 DDR3_BA0 A29 1.5-V SSTL Class I Bank address bus
N8 DDR3_BA1 A28 1.5-V SSTL Class I Bank address bus
M3 DDR3_BA2 B29 1.5-V SSTL Class I Bank address bus
K3 DDR3_CASN F28 1.5-V SSTL Class I Row address select
K9 DDR3_CKE K29 1.5-V SSTL Class I Column address select
K7 DDR3_CLK_N F26 1.5-V SSTL Class I Differential output clock
J7 DDR3_CLK_P E26 1.5-V SSTL Class I Differential output clock
L2 DDR3_CSN D30 1.5-V SSTL Class I Chip select
E7 DDR3_DM2 M22 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_DM3 K21 1.5-V SSTL Class I Write mask byte lane
E3 DDR3_DQ16 D21 1.5-V SSTL Class I Data bus byte lane 2
F7 DDR3_DQ17 E21 1.5-V SSTL Class I Data bus byte lane 2
F2 DDR3_DQ18 M21 1.5-V SSTL Class I Data bus byte lane 2
F8 DDR3_DQ19 C22 1.5-V SSTL Class I Data bus byte lane 2
H3 DDR3_DQ20 D22 1.5-V SSTL Class I Data bus byte lane 2
Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference
Schematic
Signal Name
Arria V GX
Pin Number
I/O Standard Description