Altera Arria V GX Starter Board - Manual (Page 27)

Chapter 2: Board Components 2–19
Setup Elements
November 2013 Altera Corporation Arria V GX Starter Board
Reference Manual
CPU Reset Push Button
The CPU reset push button, CPU_RESETn (S4), is an input to the Arria V GX DEV_CLRn
pin and is an open-drain I/O from the MAX V CPLD System Controller. This push
button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD
5M2210 System Controller also drives this push button during power-on-reset (POR).
MAX V Reset Push Button
The MAX V reset push button, MAX_RESETn (S3), is an input to the MAX V CPLD
5M2210 System Controller. This push button is the default reset for the CPLD logic.
Image Load Push Button
The image load push button, PGM_CONFIG (S1), is an input to the MAX V CPLD
5M2210 System Controller. This input forces a FPGA reconfiguration from the flash
memory. The location in the flash memory is based on the settings of PGM_LED[2:0],
which is controlled by the image select push button, PGM_SEL. Valid settings include
PGM_LED0
, PGM_LED1, or PGM_LED2 on the three pages in flash memory reserved for
FPGA designs.
Image Select Push Button
The program select push button, PGM_SEL (S2), is an input to the MAX V CPLD System
Controller. This push button toggles the PGM_LED[2:0]sequence that selects which
location in the flash memory is used to configure the FPGA. Refer to
Table 2–7 for the
PGM_LED[2:0] sequence definitions.
3 PCIE_PRSNT2n_x8
ON : Enable x8 presence detect
OFF : Disable x8 presence detect
ON
4 FAN_FORCE_ON
ON : Enable fan
OFF : Disable fan
OFF
Table 2–13. PCI Express Link Width DIP Switch Controls (Part 2 of 2)
Switch Schematic Signal Name Description Default