Altera Arria V GX Starter Board - Manual (Page 21)

Chapter 2: Board Components 2–13
FPGA Configuration
November 2013 Altera Corporation Arria V GX Starter Board
Reference Manual
Figure 2–5 illustrates the JTAG chain.
The JTAG DIP switch (SW2) controls the jumpers shown in Figure 2–5 . To connect a
device or interface in the chain, their corresponding switch must be in the OFF
position. Slide all the switches in the ON position to only have the FPGA in the chain.
1 The MAX V CPLD 5M2210 System Controller must be in the chain to use some of the
GUI interfaces.
Flash Memory Programming
Flash memory programming is possible through a variety of methods.
The default method is to use the factory design—Board Update Portal. This design is
an embedded webserver, which serves the Board Update Portal web page. The web
page allows you to select new FPGA designs including hardware, software, or both in
an industry-standard S-Record File (.flash) and write the design to the user hardware
page (page 1) of the flash memory over the network.
Figure 2–5. JTAG Chain
Cypress
On-Board
USB-Blaster II
GPIO
TCK
Arria V GX
FPGA
Analog
Switch
MAX V
System
Controller
HSMC
Port A
GPIO
TMS
GPIO
TDO
GPIO
GPIO
TDI
JTAG Master
GPIO
DISABLE
ENABLE
ENABLE
ENABLE
JTAG Slave
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
2.5 V
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
ALWAYS
ENABLED
(in chain)
DIP Switch
DIP Switch
DIP Switch
10-pin
JTAG Header
Flash
Memory
PCI Express
Edge
Connector
JTAG Master
PCI Express
Motherboard
TCK
TMS
TDI
TDO
Level
Shifter
2.5 V