Altera Arria V GX Starter Board User Manual
Page 29
Chapter 2: Board Components
2–21
Clock Circuitry
November 2013
Altera Corporation
Arria V GX Starter Board
Reference Manual
U5
REFCLK2_QL1_P
125.000 MHz
LVDS
(fanout buffer)
U26
Left transceiver bank
REFCLK2_QL1_N
U27
CLKINBOT_125_P
AP32
Bottom edge
CLKINBOT_125_N
AP31
CLKINTOP_125_P
A3
Top edge
CLKINTOP_125_N
B3
REFCLK2_QR1_P
U9
HSMC port A
REFCLK2_QR1_N
U8
X2
CLK_125_P
125.000 MHz
LVDS
AH17
10/100/1000 Ethernet
CLK_125_N
AG17
X1
CLK_148_P
148.500 MHz
LVDS
R26
HD-SDI video
CLK_148_N
R27
U4
Si5338A_CLK0_125_P
125.000 MHz
LVDS
(fanout buffer)
—
LVDS fanout buffer
Si5338A_CLK0_125_N
—
REFCLK1_QL0_P
409.600 MHz
LVDS
W26
SMA
REFCLK1_QL0_N
W27
REFCLK1_QR0_P
156.250 MHz
LVDS
W9
HSMC port A
REFCLK1_QR0_N
W8
Si5338A_CLK3_100_P
100.000 MHz
LVDS
(fanout buffer)
—
LVDS fanout buffer
Si5338A_CLK3_100_N
—
U3
CLKINTOP_100_P
100.000 MHz
LVDS
A19
Top edge—DDR3
CLKINTOP_100_N
A20
CLKINBOT_100_P
LVDS
AH18
Bottom edge
CLKINBOT_100_N
AG18
Table 2–14. On-Board Oscillators
Source
Schematic Signal Name
Frequency
I/O Standard
Arria V GX Pin
Number
Application
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)