beautypg.com

Altera Arria V GX Starter Board User Manual

Page 18

background image

2–10

Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Arria V GX Starter Board

November 2013

Altera Corporation

Reference Manual

L11

FSM_D7

2.5-V

FSM data bus

L15

FSM_D8

2.5-V

FSM data bus

L12

FSM_D9

2.5-V

FSM data bus

M16

FSM_D10

2.5-V

FSM data bus

L13

FSM_D11

2.5-V

FSM data bus

M15

FSM_D12

2.5-V

FSM data bus

L14

FSM_D13

2.5-V

FSM data bus

N16

FSM_D14

2.5-V

FSM data bus

M13

FSM_D15

2.5-V

FSM data bus

N15

FSM_D16

2.5-V

FSM data bus

N14

FSM_D17

2.5-V

FSM data bus

P15

FSM_D18

2.5-V

FSM data bus

P14

FSM_D19

2.5-V

FSM data bus

D13

FSM_D20

2.5-V

FSM data bus

D14

FSM_D21

2.5-V

FSM data bus

F11

FSM_D22

2.5-V

FSM data bus

J16

FSM_D23

2.5-V

FSM data bus

F12

FSM_D24

2.5-V

FSM data bus

K12

FSM_D25

2.5-V

FSM data bus

M14

FSM_D26

2.5-V

FSM data bus

N13

FSM_D27

2.5-V

FSM data bus

R1

FSM_D28

2.5-V

FSM data bus

P4

FSM_D29

2.5-V

FSM data bus

N5

FSM_D30

2.5-V

FSM data bus

P6

FSM_D31

2.5-V

FSM data bus

B8

HSMA_PRSNTN

2.5-V

HSMC port A present

D6

INT_TSD_SDA

2.5-V

Internal TSD I

2

C bus

E6

INT_TSD_SCL

2.5-V

Internal TSD I

2

C bus

C4

LTC3880_SDA_2.5V

2.5-V

1.1-V VCC core power supply to PMBus

B4

LTC3880_SCL_2.5V

2.5-V

1.1-V VCC core power supply to PMBus

B1

LTC3880_ALERT_N_2.5V

2.5-V

1.1-V VCC core power supply to PMBus

C5

LTC3880_GPIO0_N_2.5V

2.5-V

1.1-V VCC core power supply to PMBus

L6

JTAG_5M2210_TDI

2.5-V

MAX V CPLD on-board JTAG chain data in

M5

JTAG_5M2210_TDO

2.5-V

MAX V CPLD on-board JTAG chain data out

P3

JTAG_TCK

2.5-V

JTAG chain clock

P11

M570_CLOCK

2.5-V

25-MHz clock to on-board USB-Blaster II for sending
FACTORY command

P12

M570_PCIE_JTAG_EN

2.5-V

Low signal to disable the on-board USB-Blaster II when
PCI Express is the master to the JTAG chain

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 6)

Board

Reference (U15)

Schematic Signal Name

I/O Standard

Description