Altera Arria V GX Starter Board - Manual (Page 17)

Chapter 2: Board Components 2–9
MAX V CPLD 5M2210 System Controller
November 2013 Altera Corporation Arria V GX Starter Board
Reference Manual
N1 FPGA_NCONFIG 2.5-V FPGA configuration active
J4 FPGA_NSTATUS 2.5-V FPGA configuration ready
H1 FPGA_PR_DONE 2.5-V FPGA partial reconfiguration done
P2 FPGA_PR_ERROR 2.5-V FPGA partial reconfiguration error
E2 FPGA_PR_READY 2.5-V FPGA partial reconfiguration ready
F5 FPGA_PR_REQUEST 2.5-V FPGA partial reconfiguration request
E14 FSM_A0 2.5-V FSM address bus
C14 FSM_A1 2.5-V FSM address bus
C15 FSM_A2 2.5-V FSM address bus
E13 FSM_A3 2.5-V FSM address bus
E12 FSM_A4 2.5-V FSM address bus
D15 FSM_A5 2.5-V FSM address bus
F14 FSM_A6 2.5-V FSM address bus
D16 FSM_A7 2.5-V FSM address bus
F13 FSM_A8 2.5-V FSM address bus
E15 FSM_A9 2.5-V FSM address bus
E16 FSM_A10 2.5-V FSM address bus
F15 FSM_A11 2.5-V FSM address bus
G14 FSM_A12 2.5-V FSM address bus
F16 FSM_A13 2.5-V FSM address bus
G13 FSM_A14 2.5-V FSM address bus
G15 FSM_A15 2.5-V FSM address bus
G12 FSM_A16 2.5-V FSM address bus
G16 FSM_A17 2.5-V FSM address bus
H14 FSM_A18 2.5-V FSM address bus
H15 FSM_A19 2.5-V FSM address bus
H13 FSM_A20 2.5-V FSM address bus
H16 FSM_A21 2.5-V FSM address bus
J13 FSM_A22 2.5-V FSM address bus
R3 FSM_A23 2.5-V FSM address bus
P5 FSM_A24 2.5-V FSM address bus
T2 FSM_A25 2.5-V FSM address bus
J14 FSM_D0 2.5-V FSM data bus
J15 FSM_D1 2.5-V FSM data bus
K16 FSM_D2 2.5-V FSM data bus
K13 FSM_D3 2.5-V FSM data bus
K15 FSM_D4 2.5-V FSM data bus
K14 FSM_D5 2.5-V FSM data bus
L16 FSM_D6 2.5-V FSM data bus
Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 6)
Board
Reference (U15)
Schematic Signal Name I/O Standard Description