Altera Arria V GX Starter Board - Manual (Page 48)

2–40 Chapter 2: Board Components
Memory
Arria V GX Starter Board November 2013 Altera Corporation
Reference Manual
R2 DDR3_A7 L27 1.5-V SSTL Class I Address bus
T8 DDR3_A8 D27 1.5-V SSTL Class I Address bus
R3 DDR3_A9 C28 1.5-V SSTL Class I Address bus
L7 DDR3_A10 C29 1.5-V SSTL Class I Address bus
R7 DDR3_A11 D28 1.5-V SSTL Class I Address bus
N7 DDR3_A12 G27 1.5-V SSTL Class I Address bus
T3 DDR3_A13 G28 1.5-V SSTL Class I Address bus
M2 DDR3_BA0 A29 1.5-V SSTL Class I Bank address bus
N8 DDR3_BA1 A28 1.5-V SSTL Class I Bank address bus
M3 DDR3_BA2 B29 1.5-V SSTL Class I Bank address bus
K3 DDR3_CASN F28 1.5-V SSTL Class I Row address select
K9 DDR3_CKE K29 1.5-V SSTL Class I Column address select
J7 DDR3_CLK_P E26
Differential 1.5-V SSTL
Class I
Differential output clock
K7 DDR3_CLK_N F26
Differential 1.5-V SSTL
Class I
Differential output clock
L2 DDR3_CSN D30 1.5-V SSTL Class I Chip select
E7 DDR3_DM0 M25 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_DM1 M23 1.5-V SSTL Class I Write mask byte lane
E3 DDR3_DQ0 G24 1.5-V SSTL Class I Data bus byte lane 0
F7 DDR3_DQ1 H24 1.5-V SSTL Class I Data bus byte lane 0
F2 DDR3_DQ2 M24 1.5-V SSTL Class I Data bus byte lane 0
F8 DDR3_DQ3 A26 1.5-V SSTL Class I Data bus byte lane 0
H3 DDR3_DQ4 A25 1.5-V SSTL Class I Data bus byte lane 0
H8 DDR3_DQ5 C25 1.5-V SSTL Class I Data bus byte lane 0
G2 DDR3_DQ6 B26 1.5-V SSTL Class I Data bus byte lane 0
H7 DDR3_DQ7 C26 1.5-V SSTL Class I Data bus byte lane 0
D7 DDR3_DQ8 H23 1.5-V SSTL Class I Data bus byte lane 1
C3 DDR3_DQ9 J23 1.5-V SSTL Class I Data bus byte lane 1
C8 DDR3_DQ10 K24 1.5-V SSTL Class I Data bus byte lane 1
C2 DDR3_DQ11 B24 1.5-V SSTL Class I Data bus byte lane 1
A7 DDR3_DQ12 C23 1.5-V SSTL Class I Data bus byte lane 1
A2 DDR3_DQ13 D23 1.5-V SSTL Class I Data bus byte lane 1
B8 DDR3_DQ14 D24 1.5-V SSTL Class I Data bus byte lane 1
A3 DDR3_DQ15 E24 1.5-V SSTL Class I Data bus byte lane 1
F3 DDR3_DQS_P0 F25
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 0
G3 DDR3_DQS_N0 G25
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 0
Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board Reference
Schematic
Signal Name
Arria V GX
Pin Number
I/O Standard Description