Altera Arria V GX Starter Board - Manual (Page 11)

Chapter 2: Board Components 2–3
Board Overview
November 2013 Altera Corporation Arria V GX Starter Board
Reference Manual
J14 On-Board USB-Blaster II
USB interface for programming and debugging the FPGA through
embedded USB-Blaster II JTAG via a type-B USB cable.
SW4 Board settings DIP switch
Controls the MAX V CPLD 5M2210 System Controller functions such
as clock enable, SMA clock input control, and which image to load
from flash memory at power-up.
SW1 PCI Express DIP switch
Controls the PCI Express lane width by connecting prsnt pins
together on the PCI Express edge connector.
S2 Image select push button
Toggles the configuration LEDs which selects the program image that
loads from flash memory to the FPGA.
S1 Load image push button
Load image from flash memory to the FGPA based on the
configuration LED setting.
D8, D9 System Console LEDs
Indicate transmit or receive activity of the System Console USB
interface. The TX and RX LEDs would flicker if the link is in use and
active.
D12 Configuration done LED Illuminates when the FPGA is configured.
D11 Load LED
Illuminates when the MAX V CPLD 5M2210 System Controller is
actively configuring the FPGA.
D10 Error LED Illuminates when the FPGA configuration from flash memory fails.
D30 Power LED Illuminates when 5.0-V power is present.
D24, D25, D26 Configuration LEDs
Illuminates to show the LED sequence that determines which flash
memory image loads to the FPGA when you press the PGM_SEL push
button.
D2, D3, D4, D5,
D33
Ethernet LEDs Shows the connection speed as well as transmit or receive activity.
D13, D14 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.
D15 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D16, D17, D18,
D19
PCI Express link LEDs
You can configure these LEDs to indicate the PCI Express link width
(x1, x4, x8) and Gen2 link.
Clock Circuitry
U4 Quad-output oscillator
Programmable oscillator with default frequencies of 125 MHz,
409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is
programmable using the clock control GUI running on the MAX V
CPLD 5M2210 System Controller.
X1 148.5-MHz oscillator
148.500-MHz voltage controlled crystal oscillator for serial digital
interface (SDI) video. This oscillator is programmable to any frequency
between 20–810 MHz using the clock control GUI running on the
MAX V CPLD 5M2210 System Controller.
X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.
X3 100-MHz oscillator
100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System
Controller.
X2 125-MHz oscillator 125.000 MHz crystal oscillator for Gigabit Ethernet.
J7, J8 Clock input SMAs
Drive LVPECL-compatible clock inputs into the clock multiplexer buffer
(U5).
J6 Clock output SMA Drive out 2.5-V CMOS clock output from the FPGA.
Table 2–1. Arria V GX Starter Board Components (Part 2 of 3)
Board Reference Type Description