Altera Stratix V GX FPGA Development Board - Manual (Page 74)

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Document Revision History
Stratix V GX FPGA Development Board October 2014 Altera Corporation
Reference Manual
October 2011 1.1
■ Updated the transceiver speed to 12.5 Gbps.
■ Revised the FPGA device pin numbers that connect to the on-board oscillator signals:
■ CLKINBOT_P0 : Changed from AV29 to AH 22
■ CLKINBOT_N0 : Changed from AW29 to AJ22
■ CLK_125_P : Changed from AH22 to AV29
■ CLK_125_N : Changed from AJ22 to AW29
■ Revised the FPGA device pin number that connects to the PCI Express SMB clock signal,
PCIE_SMBCLK
—changed from AP34 to AN33.
■ Revised the FPGA device pin numbers that connect to the Ethernet PHY signals:
■ ENET_RX_P : Changed from AU24 to AP34
■ ENET_RX_N : Changed from AU25 to AR34
■ Corrected the FPGA device pin numbers that connect to the SDI video output/input
interface signals:
■ SDI_TX_P : Changed from F38 to E36
■ SDI_TX_N : Changed from F39 to E37
■ SDI_RX_P : Changed from E36 to F38
■ SDI_RX_N : Changed from E37 to F39
■ Updated Figure 2–5.
■ Updated Figure 2–10.
August 2011 1.0 Initial release.
Date Version Changes