Altera Stratix V GX FPGA Development Board - Manual (Page 64)

2–56 Chapter 2: Board Components
Memory
Stratix V GX FPGA Development Board October 2014 Altera Corporation
Reference Manual
U11.E7 FM_D31 1.8-V AT24 Data bus
U11.G7 FM_D30 1.8-V AV25 Data bus
U11.H5 FM_D29 1.8-V AW25 Data bus
U11.F5 FM_D28 1.8-V AL25 Data bus
U11.F4 FM_D27 1.8-V AL24 Data bus
U11.F3 FM_D26 1.8-V AJ24 Data bus
U11.E3 FM_D25 1.8-V AK24 Data bus
U11.E1 FM_D24 1.8-V AH24 Data bus
U11.H7 FM_D23 1.8-V AG24 Data bus
U11.G6 FM_D22 1.8-V AD24 Data bus
U11.G5 FM_D21 1.8-V AE24 Data bus
U11.E5 FM_D20 1.8-V AE25 Data bus
U11.E4 FM_D19 1.8-V AF25 Data bus
U11.G3 FM_D18 1.8-V AB24 Data bus
U11.E2 FM_D17 1.8-V AC24 Data bus
U11.F2 FM_D16 1.8-V AN24 Data bus
U10.E7 FM_D15 1.8-V AP24 Data bus
U10.G7 FM_D14 1.8-V AM25 Data bus
U10.H5 FM_D13 1.8-V AN25 Data bus
U10.F5 FM_D12 1.8-V AL20 Data bus
U10.F4 FM_D11 1.8-V AL21 Data bus
U10.F3 FM_D10 1.8-V AJ20 Data bus
U10.E3 FM_D9 1.8-V AJ21 Data bus
U10.E1 FM_D8 1.8-V AK21 Data bus
U10.H7 FM_D7 1.8-V AL22 Data bus
U10.G6 FM_D6 1.8-V AE20 Data bus
U10.G5 FM_D5 1.8-V AE21 Data bus
U10.E5 FM_D4 1.8-V AH21 Data bus
U10.E4 FM_D3 1.8-V AG21 Data bus
U10.G3 FM_D2 1.8-V AD20 Data bus
U10.E2 FM_D1 1.8-V AD21 Data bus
U10.F2 FM_D0 1.8-V AN21 Data bus
E6 FLASH_CLK 1.8-V AM8 Clock
U10.B4 FLASH_CEn0 1.8-V AV14 Chip enable
U11.B4 FLASH_CEn1 1.8-V AW13 Chip enable
F8 FLASH_OEn 1.8-V AJ7 Output enable
F6 FLASH_ADVn 1.8-V AP7 Address valid
U10.F7 FLASH_RDYBSYn0 1.8-V AL6 Ready
Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference
(U10, U11)
Schematic Signal
Name
I/O Standard
Stratix V GX FPGA
Device Pin
Number
Description