Altera Stratix V GX FPGA Development Board User Manual
Page 23
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Chapter 2: Board Components
2–15
Configuration, Status, and Setup Elements
October 2014
Altera Corporation
Stratix V GX FPGA Development Board
Reference Manual
1
By default, the on-board USB-Blaster II clocks TCK at 24 MHz. For the on-board
USB-Blaster II to function correctly, you must set the Quartus II clock constraint on the
internal_tck
input signal to 24 MHz.
System Console USB Interface
The System Console USB interface is a fast parallel interface. Together with the soft
logic supplied by Altera, this interface provides a System Console master for debug
access.
The System Console controls the debug master via signals shown in
fast access to an Avalon
®
Memory-Mapped (Avalon-MM) master bus that the Qsys
system integration tool generates.
f
For more information about the System Console, refer to the
chapter in volume 3 of the Quartus II Handbook.
lists the System Console USB interface pin connections relative to the FPGA.
Flash Programming
Flash programming is possible through a variety of methods using the Stratix V GX
FPGA device.
The first method is to use the factory design called the Board Update Portal. This
design is an embedded web server, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash over the network.
Table 2–8. System Console USB Interface Pin Connections
Stratix V GX FPGA Device Pin Number
Schematic Signal Name
Direction
Note
AV28
usb_clk
input
48 MHz
H34
usb_reset_n
input
—
G32, G33, F32, E32, A37, A36, C34, A35
usb_data[7:0]
bidirectional
G32(MSB), A35 (LSB)
N34
usb_full
output
—
P34
usb_empty
output
—
J33
usb_wr_n
input
—
K33
usb_rd_n
input
—
E33
usb_oe_n
input
—
G34, K34
usb_addr
bidirectional
Reserved
J34
usb_scl
bidirectional
—
F33
usb_sda
bidirectional
—