Altera Stratix V GX FPGA Development Board - Manual (Page 56)

2–48 Chapter 2: Board Components
Memory
Stratix V GX FPGA Development Board October 2014 Altera Corporation
Reference Manual
U28.H7 DDR3_DQ7 1.5-V SSTL Class I G28 Data bus byte lane 0
U28.E7 DDR3_DM0 1.5-V SSTL Class I A29 Write mask byte lane 0
U28.F3 DDR3_DQS_P0 1.5-V SSTL Class I H29 Data strobe P byte lane 0
U28.G3 DDR3_DQS_N0 1.5-V SSTL Class I G29 Data strobe N byte lane 0
U28.D7 DDR3_DQ8 1.5-V SSTL Class I K28 Data bus byte lane 1
U28.C3 DDR3_DQ9 1.5-V SSTL Class I M29 Data bus byte lane 1
U28.C8 DDR3_DQ10 1.5-V SSTL Class I L28 Data bus byte lane 1
U28.C2 DDR3_DQ11 1.5-V SSTL Class I R29 Data bus byte lane 1
U28.A7 DDR3_DQ12 1.5-V SSTL Class I P29 Data bus byte lane 1
U28.A2 DDR3_DQ13 1.5-V SSTL Class I V29 Data bus byte lane 1
U28.B8 DDR3_DQ14 1.5-V SSTL Class I N28 Data bus byte lane 1
U28.A3 DDR3_DQ15 1.5-V SSTL Class I U29 Data bus byte lane 1
U28.D3 DDR3_DM1 1.5-V SSTL Class I J28 Write mask byte lane 1
U28.C7 DDR3_DQS_P1 1.5-V SSTL Class I U30 Data strobe P byte lane 1
U28.B7 DDR3DQS_N1 1.5-V SSTL Class I T30 Data strobe N byte lane 1
U23.E3 DDR3_DQ16 1.5-V SSTL Class I G26 Data bus byte lane 2
U23.F7 DDR3_DQ17 1.5-V SSTL Class I D27 Data bus byte lane 2
U23.F2 DDR3_DQ18 1.5-V SSTL Class I F26 Data bus byte lane 2
U23.F8 DDR3_DQ19 1.5-V SSTL Class I C27 Data bus byte lane 2
U23.H3 DDR3_DQ20 1.5-V SSTL Class I C26 Data bus byte lane 2
U23.H8 DDR3_DQ21 1.5-V SSTL Class I J26 Data bus byte lane 2
U23.G2 DDR3_DQ22 1.5-V SSTL Class I E27 Data bus byte lane 2
U23.H7 DDR3_DQ23 1.5-V SSTL Class I H26 Data bus byte lane 2
U23.E7 DDR3_DM2 1.5-V SSTL Class I A26 Write mask byte lane 2
U23.F3 DDR3_DQS_P2 1.5-V SSTL Class I G27 Data strobe P byte lane 2
U28.G3 DDR3_DQS_N2 1.5-V SSTL Class I F27 Data strobe N byte lane 2
U23.D7 DDR3_DQ24 1.5-V SSTL Class I J27 Data bus byte lane 3
U23.C3 DDR3_DQ25 1.5-V SSTL Class I N27 Data bus byte lane 3
U23.C8 DDR3_DQ26 1.5-V SSTL Class I T27 Data bus byte lane 3
U23.C2 DDR3_DQ27 1.5-V SSTL Class I M27 Data bus byte lane 3
U23.A7 DDR3_DQ28 1.5-V SSTL Class I U26 Data bus byte lane 3
U23.A2 DDR3_DQ29 1.5-V SSTL Class I P28 Data bus byte lane 3
U23.B8 DDR3_DQ30 1.5-V SSTL Class I U27 Data bus byte lane 3
U23.A3 DDR3_DQ31 1.5-V SSTL Class I R27 Data bus byte lane 3
U23.D3 DDR3_DM3 1.5-V SSTL Class I L27 Write mask byte lane 3
U23.C7 DDR3_DQS_P3 1.5-V SSTL Class I U28 Data strobe P byte lane 3
U23.B7 DDR3_DQS_N3 1.5-V SSTL Class I T28 Data strobe N byte lane 3
U21.E3 DDR3_DQ32 1.5-V SSTL Class I B25 Data bus byte lane 4
Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board Reference
(U12, U17, U21,
U23, U28)
Schematic Signal
Name
I/O Standard
Stratix V GX FPGA
Device Pin Number
Description