Altera Stratix V GX FPGA Development Board - Manual (Page 39)

Chapter 2: Board Components 2–31
Components and Interfaces
October 2014 Altera Corporation Stratix V GX FPGA Development Board
Reference Manual
Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Stratix V GX FPGA device. The development board supports the
following communication ports:
■ PCI Express
■ 10/100/1000 Ethernet
■ HSMC
■ SDI Video Output
■ 40G QSFP Module
PCI Express
The Stratix V GX FPGA development board is designed to fit entirely into a PC
motherboard with a ×8 PCI Express slot that can accommodate a full height short
form factor add-in card. This interface uses the Stratix V GX FPGA device's PCI
Express hard IP block, saving logic resources for the user logic application.
f For more information on using the PCI Express hard IP block, refer to the IP Compiler
for PCI Express User Guide .
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to
×8 as well as the connection speed of Gen1 at 2.5 Gbps/lane, Gen2 at 5.0 Gbps/lane,
or Gen3 at 8.0 Gbps/lane for a maximum of 64 Gbps full-duplex bandwidth.
The power for the board can be sourced entirely from the PCI Express edge connector
when installed into a PC motherboard. Although the board can also be powered by a
laptop power supply for use on a lab bench, it is not recommended to power from
both supplies at the same time. Ideal diode power sharing devices have been
designed into this board to prevent damages or back-current from one supply to the
other.
The PCIE_REFCLK_P/N signal is a 100-MHz differential input that is driven from the PC
motherboard to the board through the PCI Express edge connector. This signal
connects directly to a Stratix V GX FPGA REFCLK input pin pair using DC coupling.
This clock is terminated on the motherboard and therefore, no on-board termination is
required. This clock can have spread-spectrum properties that change its period
between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic
(HCSL).