Altera Stratix V GX FPGA Development Board User Manual
Page 7
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Chapter 1: Overview
1–3
Board Component Blocks
October 2014
Altera Corporation
Stratix V GX FPGA Development Board
Reference Manual
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Communication Ports
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PCI Express (PCIe) x8 edge connector
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Two HSMC ports
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One universal HSMC port A
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One DQS-type HSMC port B
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SMB for SDI input and output
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QSFP
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USB 2.0
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Gigabit Ethernet
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LCD header
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General User I/O
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16 user LEDs
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Two-line character LCD display
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Six configuration status LEDs
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One transmit/receive LED (TX/RX) per HSMC interface
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Five PCI Express LEDs
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Four Ethernet LEDs
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Push Buttons and DIP Switches
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One CPU reset push button
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Three general user push buttons
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Two configuration push buttons
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Eight user DIP switches
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Four MAX
V control DIP switches
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Power
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19-V (laptop) DC input
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PCI Express edge connector power
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On-Board power measurement circuitry
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System Monitoring
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Power—voltage, current, wattage
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Temperature—FPGA die, local board
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Mechanical
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PCI Express short form factor
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PCI Express chassis or bench-top operation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)