Altera Stratix V GX FPGA Development Board - Manual (Page 5)

October 2014 Altera Corporation Stratix V GX FPGA Development Board
Reference Manual
1. Overview
This document describes the hardware features of the Stratix ® V GX FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Stratix V GX FPGA development board provides a hardware platform for
developing and prototyping high-performance and high-bandwidth application
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of Stratix V GX FPGA designs.
Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional
functionality via a variety of HSMC cards available from both Altera and various
partners.
f To see a list of the latest HSMC cards available or to download a copy of the HSMC
specification, refer to the
Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the PCI Express hard IP
implementation, partial reconfiguration, and programmable power technology
ensure that designs implemented in the Stratix V GX FPGAs operate faster, with
lower power than in previous FPGA families.
f For more information on the following topics, refer to the respective documents:
■ Stratix V device family, refer to the Stratix V Device Handbook .
■ PCI Express hard IP implementation, refer to the Stratix V Hard IP for PCI Express
User Guide .
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification .