Configuration, status, and setup elements, Configuration, Fpga programming over on-board usb-blaster ii – Altera Stratix V GX FPGA Development Board User Manual
Page 20: Configuration, status, and setup elements –12, Configuration –12, Fpga programming over on-board usb-blaster ii –12
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2–12
Chapter 2: Board Components
Configuration, Status, and Setup Elements
Stratix V GX FPGA Development Board
October 2014
Altera Corporation
Reference Manual
lists the MAX V CPLD System Controller component reference and
manufacturing information.
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX V CPLD System Controller
device programming methods that the Stratix V GX FPGA development board
supports.
The Stratix V GX FPGA development board supports three configuration methods:
■
On-Board USB-Blaster II is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied
micro-USB cable.
■
Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the program load push button (S2).
■
External USB-Blaster for configuring the FPGA using the external USB-Blaster.
FPGA Programming over On-Board USB-Blaster II
The on-board USB-Blaster II is implemented using a micro-USB type-B connector (J7),
a USB 2.0 PHY device, and an Altera MAX II CPLD EPM570GM100 (U14). This allows
the configuration of the FPGA using a USB cable which connects directly between the
USB port on the board (J7) and a USB port on a PC running the Quartus II software.
The on-board USB-Blaster II normally masters the JTAG chain.
f
For more information about the on-board USB-Blaster II, refe
page of the Altera Wiki website.
SI571_EN
D4
—
2.5-V
Si571 programmable VCXO enable
TSENSE_ALERTn
B5
—
2.5-V
Temperature monitor alert
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 6 of 6)
Schematic Signal Name
MAX V CPLD
Pin Number
Stratix V GX FPGA
Pin Number
I/O
Standard
Description
Table 2–6. MAX V CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference
Description
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U4
MAX V CPLD 2210 LE
256FBGA LF 1.8V VCCINT
Altera
Corporation
5M2210ZF256C4N