Altera Stratix V GX FPGA Development Board - Manual (Page 63)

Chapter 2: Board Components 2–55
Memory
October 2014 Altera Corporation Stratix V GX FPGA Development Board
Reference Manual
Flash
The development board has two 512-Mb CFI-compatible synchronous flash device for
non-volatile storage of FPGA configuration data, board information, test application
data, and user code space.
Each interface has a 16-bit data bus and the two devices combined allow for x32 FPP
configuration. This device is part of the shared flash and MAX (FM) bus, which
connects to the flash memory and MAX V CPLD System Controller.
Each 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps per device. The write performance is 270 µs for a single
word and 310 µs for a 32-word buffer. The erase time is 800 ms for a 128 K parameter
block.
Table 2–56 lists the flash pin assignments, signal names, and functions.
Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference
(U10, U11)
Schematic Signal
Name
I/O Standard
Stratix V GX FPGA
Device Pin
Number
Description
B8 FM_A26 1.8-V AJ17 Address bus (for pin-compatible 1 Gb devices)
B6 FM_A25 1.8-V AP21 Address bus
H8 FM_A24 1.8-V AH16 Address bus
G1 FM_A23 1.8-V AE17 Address bus
A8 FM_A22 1.8-V AE16 Address bus
C8 FM_A21 1.8-V AK17 Address bus
C7 FM_A20 1.8-V AL17 Address bus
B7 FM_A19 1.8-V AT6 Address bus
A7 FM_A18 1.8-V AU6 Address bus
D8 FM_A17 1.8-V AV17 Address bus
D7 FM_A16 1.8-V AW17 Address bus
C5 FM_A15 1.8-V AV16 Address bus
B5 FM_A14 1.8-V AW16 Address bus
A5 FM_A13 1.8-V AU17 Address bus
C4 FM_A12 1.8-V AU16 Address bus
D3 FM_A11 1.8-V AR17 Address bus
C3 FM_A10 1.8-V AT17 Address bus
B3 FM_A9 1.8-V AN16 Address bus
A3 FM_A8 1.8-V AP16 Address bus
C2 FM_A7 1.8-V AM17 Address bus
A2 FM_A6 1.8-V AN17 Address bus
D2 FM_A5 1.8-V AG16 Address bus
D1 FM_A4 1.8-V AF16 Address bus
C1 FM_A3 1.8-V AL16 Address bus
B1 FM_A2 1.8-V AM16 Address bus
A1 FM_A1 1.8-V AV19 Address bus