Altera Stratix V GX FPGA Development Board - Manual (Page 57)

Chapter 2: Board Components 2–49
Memory
October 2014 Altera Corporation Stratix V GX FPGA Development Board
Reference Manual
U21.F7 DDR3_DQ33 1.5-V SSTL Class I F24 Data bus byte lane 4
U21.F2 DDR3_DQ34 1.5-V SSTL Class I C25 Data bus byte lane 4
U21.F8 DDR3_DQ35 1.5-V SSTL Class I G24 Data bus byte lane 4
U21.H3 DDR3_DQ36 1.5-V SSTL Class I D24 Data bus byte lane 4
U21.H8 DDR3_DQ37 1.5-V SSTL Class I H25 Data bus byte lane 4
U21.G2 DDR3_DQ38 1.5-V SSTL Class I C24 Data bus byte lane 4
U21.H7 DDR3_DQ39 1.5-V SSTL Class I G25 Data bus byte lane 4
U21.E7 DDR3_DM4 1.5-V SSTL Class I A25 Write mask byte lane 4
U21.F3 DDR3DQS_P4 1.5-V SSTL Class I E24 Data strobe P byte lane 4
U21.G3 DDR3_DQS_N4 1.5-V SSTL Class I E25 Data strobe N byte lane 4
U21.D7 DDR3_DQ40 1.5-V SSTL Class I J25 Data bus byte lane 5
U21.C3 DDR3_DQ41 1.5-V SSTL Class I N26 Data bus byte lane 5
U21.C8 DDR3_DQ42 1.5-V SSTL Class I L26 Data bus byte lane 5
U21.C2 DDR3_DQ43 1.5-V SSTL Class I P26 Data bus byte lane 5
U21.A7 DDR3_DQ44 1.5-V SSTL Class I P25 Data bus byte lane 5
U21.A2 DDR3_DQ45 1.5-V SSTL Class I T25 Data bus byte lane 5
U21.B8 DDR3_DQ46 1.5-V SSTL Class I N25 Data bus byte lane 5
U21.A3 DDR3_DQ47 1.5-V SSTL Class I U25 Data bus byte lane 5
U21.D3 DDR3_DM5 1.5-V SSTL Class I K25 Write mask byte lane 5
U21.C7 DDR3_DQS_P5 1.5-V SSTL Class I R25 Data strobe P byte lane 5
U21.B7 DDR3_DQS_N5 1.5-V SSTL Class I R26 Data strobe N byte lane 5
U17.E3 DDR3_DQ48 1.5-V SSTL Class I H22 Data bus byte lane 6
U17.F7 DDR3_DQ49 1.5-V SSTL Class I B23 Data bus byte lane 6
U17.F2 DDR3_DQ50 1.5-V SSTL Class I G22 Data bus byte lane 6
U17.F8 DDR3_DQ51 1.5-V SSTL Class I G23 Data bus byte lane 6
U17.H3 DDR3_DQ52 1.5-V SSTL Class I D22 Data bus byte lane 6
U17.H8 DDR3_DQ53 1.5-V SSTL Class I H23 Data bus byte lane 6
U17.G2 DDR3_DQ54 1.5-V SSTL Class I C22 Data bus byte lane 6
U17.H7 DDR3_DQ55 1.5-V SSTL Class I A23 Data bus byte lane 6
U17.E7 DDR3_DM6 1.5-V SSTL Class I A22 Write mask byte lane 6
U17.F3 DDR3_DQS_P6 1.5-V SSTL Class I F23 Data strobe P byte lane 6
U17.G3 DDR3_DQS_N6 1.5-V SSTL Class I E23 Data strobe N byte lane 6
U17.D7 DDR3_DQ56 1.5-V SSTL Class I A20 Data bus byte lane 7
U17.C3 DDR3_DQ57 1.5-V SSTL Class I C20 Data bus byte lane 7
U17.C8 DDR3_DQ58 1.5-V SSTL Class I F20 Data bus byte lane 7
U17.C2 DDR3_DQ59 1.5-V SSTL Class I C21 Data bus byte lane 7
U17.A7 DDR3_DQ60 1.5-V SSTL Class I H20 Data bus byte lane 7
U17.A2 DDR3_DQ61 1.5-V SSTL Class I D21 Data bus byte lane 7
Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference
(U12, U17, U21,
U23, U28)
Schematic Signal
Name
I/O Standard
Stratix V GX FPGA
Device Pin Number
Description