Altera Arria V GZ Avalon-ST - Manual (Page 87)

Signal Direction Description
For example, if you are using the Hard IP instance in the bottom
left corner of the device, you must connect
pin_perst
to
NPERSL0
.
For maximum use of the Arria V GZ V device, Altera
recommends that you use the bottom left Hard IP first. This is
the only location that supports CvP over a PCIe link. If your
design does not require CvP, you may select other Hard IP
blocks.
Refer to the appropriate device pinout for correct pin assignment
for more detailed information about these pins. The PCI Express
Card Electromechanical Specification 2.0 specifies this pin
requires 3.3 V. You can drive this 3.3V signal to the
nPERST*
even if the V
VCCPGM
of the bank is not 3.3V if the following 2
conditions are met:
• The input signal meets the V
IH
and V
IL
specification for
LVTTL.
• The input signal meets the overshoot specification for 100°C
operation as defined in the device handbook.
Figure 5-34: Reset and Link Training Timing Relationships
The following figure illustrates the timing relationship between
npor
and the LTSSM L0 state.
npor
IO_POF_Load
PCIe_LinkTraining_Enumeration
dl_ltssm[4:0]
detect detect.active polling.active L0
Note: To meet the 100 ms system configuration time, you must use the fast passive parallel configuration
scheme with CvP and a 32-bit data width (FPP x32) or use the CvP in autonomous mode.
Table 5-7: Status and Link Training Signals
Signal Direction Description
serdes_pll_locked Output When asserted, indicates that the PLL that generates the
coreclkout_hip
clock signal is locked. In pipe simulation mode
this signal is always asserted.
UG-01127_avst
2014.12.15
Reset, Status, and Link Training Signals 5-35
Interfaces and Signal Descriptions Altera Corporation
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