Altera Arria V GZ Avalon-ST - Manual (Page 160)

Figure 9-2: Correctable Error Status Register
The default value of all the bits of this register is 0. An error status bit that is set indicates that the error
condition it represents has been detected. Software may clear the error status by writing a 1 to the
appropriate bit.
Rsvd Rsvd Rsvd
Header Log Overflow Status
Corrected Internal Error Status
Advisory Non-Fatal Error Status
Replay Timer Timeout Status
REPLAY_NUM Rollover Status
Bad DLLP Status
Bad TLP Status
Receiver Error Status
16 15 14 13 12 11 9 8 7 6 5 1 0 31
9-8 Uncorrectable and Correctable Error Status Bits
UG-01127_avst
2014.12.15
Altera Corporation Error Handling
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