Altera Arria V GZ Avalon-ST - Manual (Page 147)

Figure 8-1: MSI Handler Block
MSI Handler
Block
app_msi_req
app_msi_ack
app_msi_tc[2:0]
app_msi_num[4:0]
pex_msi_num
app_int_sts
cfg_msicsr[15:0]
The following figure illustrates a possible implementation of the MSI handler block with a per vector
enable bit. A global Application Layer interrupt enable can also be implemented instead of this per vector
MSI.
Figure 8-2: Example Implementation of the MSI Handler Block
app_int_en0
app_int_sts0
app_msi_req0
app_int_en1
app_int_sts1
app_msi_req1
app_int_sts
MSI
Arbitration
msi_enable & Master Enable
app_msi_req
app_msi_ack
Vector 1
Vector 0
IRQ
Generation
App Layer
IRQ
Generation
App Layer
R/W
R/W
There are 32 possible MSI messages. The number of messages requested by a particular component does
not necessarily correspond to the number of messages allocated. For example, in the following figure, the
Endpoint requests eight MSIs but is only allocated two. In this case, you must design the Application
Layer to use only two allocated messages.
8-2 MSI Interrupts
UG-01127_avst
2014.08.18
Altera Corporation Interrupts
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