Altera Arria V GZ Avalon-ST - Manual (Page 137)

Bits Register Description Reset Value Access
[5] When set, indicates a configuration error has been detected in
CvP mode which is reported as correctable. This bit is set
whenever a
CVP_CONFIG_ERROR
occurs while in
CVP_MODE
.
0 RW1CS
[4:2] Reserved. 0 RO
[1] When set, the retry buffer correctable ECC error status indicates
an error.
0 RW1CS
[0] When set, the RX buffer correctable ECC error status indicates an
error.
0 RW1CS
Related Information
PCI Express Base Specification 2.1 or 3.0
6-16 Correctable Internal Error Status Register
UG-01127_avst
2014.08.18
Altera Corporation Registers
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